[PATCH 1/2] added support for hevc encoder
Himanshu Nayak
himanshu.nayak at amd.com
Tue Mar 19 12:59:14 UTC 2024
---
lib/amdgpu/amd_mmd_decode_messages.h | 373 ++++++++++-
lib/amdgpu/amd_mmd_frame.h | 771 +++++++++++++++++++++++
tests/amdgpu/amd_vcn.c | 828 ++-----------------------
tests/amdgpu/amd_vcn_common.c | 727 ++++++++++++++++++++++
tests/amdgpu/amd_vcn_common.h | 187 ++++++
tests/amdgpu/amd_vcn_hevc.c | 887 +++++++++++++++++++++++++++
tests/amdgpu/amd_vcn_hevc.h | 89 +++
7 files changed, 3075 insertions(+), 787 deletions(-)
create mode 100644 tests/amdgpu/amd_vcn_common.c
create mode 100644 tests/amdgpu/amd_vcn_common.h
create mode 100644 tests/amdgpu/amd_vcn_hevc.c
create mode 100644 tests/amdgpu/amd_vcn_hevc.h
diff --git a/lib/amdgpu/amd_mmd_decode_messages.h b/lib/amdgpu/amd_mmd_decode_messages.h
index 22f223aaf..c30202411 100644
--- a/lib/amdgpu/amd_mmd_decode_messages.h
+++ b/lib/amdgpu/amd_mmd_decode_messages.h
@@ -324,6 +324,123 @@ static const uint8_t uvd_bitstream[] ={
0xeb,0xae,0xba,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
+static const uint8_t hevc_bitstream[] ={
+ 0x00,0x00,0x00,0x01,0x26,0x01,0xAD,0xC0,0x37,0x12,0x32,0xE0,0x72,0x3D,0xA8,0x69,
+ 0x4D,0x13,0xB7,0x96,0xB6,0x88,0x98,0x91,0x51,0x41,0xAE,0x7B,0x2C,0x61,0xF0,0xE4,
+ 0xE0,0x37,0x42,0x4F,0x5A,0x44,0x6C,0xE2,0x34,0x0D,0x69,0x57,0x92,0x3A,0x00,0x03,
+ 0x64,0xA5,0xCB,0x30,0xEF,0x94,0xBA,0x41,0x73,0x30,0x1A,0x5D,0x0E,0x61,0x22,0x19,
+ 0x56,0xDC,0x3D,0xC3,0xFC,0xA3,0xAA,0xAE,0xE2,0x25,0xA2,0xEA,0x93,0x0A,0xAC,0xF9,
+ 0xA0,0x15,0x23,0x60,0x4C,0x5B,0x15,0xC4,0xD2,0x6B,0xD9,0x9A,0xC7,0x08,0xDC,0x7D,
+ 0xF6,0xF9,0xE0,0x51,0xBD,0x88,0x0F,0xBA,0x63,0x0E,0x3C,0x8A,0x6D,0xD4,0x81,0x23,
+ 0x5C,0xA6,0x07,0x74,0x34,0x01,0xBA,0xA0,0x73,0xA6,0x5F,0xB1,0x5E,0xCF,0xE9,0xB9,
+ 0xE6,0x23,0x16,0xD9,0xC6,0x56,0xC3,0x37,0x90,0x60,0x2D,0x7F,0x05,0xAA,0x49,0x20,
+ 0xBA,0x20,0x41,0x22,0x12,0xAF,0x1F,0xE8,0x2F,0x56,0xB1,0x41,0xE0,0xBF,0x51,0xE3,
+ 0xA6,0x28,0xD1,0xD9,0xFC,0xE8,0x5C,0xF1,0xD5,0x0C,0x48,0x5A,0x79,0x96,0xE2,0xBB,
+ 0x40,0x4B,0xCD,0x01,0x25,0x1E,0x37,0xE3,0x2D,0x27,0xB2,0x15,0xD6,0x7B,0x96,0xE2,
+ 0x31,0xA6,0xEF,0x84,0x55,0x52,0xC9,0x18,0xFA,0x15,0x7A,0x42,0xC4,0x49,0x32,0x7F,
+ 0xBC,0xFF,0x5E,0x49,0x57,0x1A,0xD3,0x17,0x27,0x64,0x19,0x69,0x26,0x5B,0x27,0x59,
+ 0xA9,0xCE,0xA5,0xB9,0xC4,0xA5,0xE2,0x53,0x4A,0x2D,0x23,0x25,0x1D,0x2E,0x69,0x8B,
+ 0x8A,0x2E,0xC9,0x6C,0xC2,0xF6,0xC1,0x33,0x04,0x08,0x2A,0x83,0x55,0xFE,0x73,0xF3,
+ 0x22,0x1E,0x97,0x2C,0x1B,0x39,0x2F,0x5E,0x2B,0x92,0x34,0xE3,0x57,0x15,0x09,0x0D,
+ 0xA7,0x30,0xB2,0xDA,0x31,0xE3,0xEF,0x4F,0x60,0x2C,0x92,0x1C,0x21,0x01,0xA3,0x7C,
+ 0xC0,0x3B,0xB3,0x88,0xDD,0x9B,0xBD,0xC3,0xF9,0x6F,0xD4,0xAF,0xEE,0x57,0x84,0x6B,
+ 0xDC,0xC6,0xDF,0x2C,0xE0,0x74,0x94,0x15,0xB9,0xCF,0x57,0x18,0x8B,0x0D,0xCC,0x25,
+ 0x8A,0x9E,0x3D,0x4D,0x18,0xE7,0x54,0x52,0xB7,0xAA,0x19,0x55,0xF5,0x6C,0xF3,0xCF,
+ 0xDC,0x0E,0xFC,0x52,0x8D,0xCE,0x77,0x0E,0xDC,0x29,0x71,0x1E,0xE9,0x45,0x25,0xBF,
+ 0xC1,0x62,0x6E,0x48,0xFC,0x67,0xC8,0x4F,0xD4,0xAB,0xB7,0x3D,0x4C,0xF9,0xFD,0xF3,
+ 0x5A,0x31,0x20,0xEF,0x7B,0x69,0x8F,0xC0,0xCE,0x79,0x43,0xBC,0x2D,0xA4,0xB4,0x46,
+ 0x72,0x6C,0x60,0x8D,0x59,0x05,0x24,0xCE,0x6B,0x99,0x92,0xEE,0x73,0x05,0x84,0x3B,
+ 0xFC,0xEC,0xF2,0xB7,0x50,0x1D,0x40,0x76,0x42,0xD5,0x25,0x41,0xFE,0x40,0x9B,0x2E,
+ 0x1C,0x57,0xE3,0x3E,0x21,0x6B,0x47,0x13,0x27,0x2D,0xA5,0x21,0x1C,0x07,0xE0,0x77,
+ 0x29,0x38,0x59,0x76,0x27,0x94,0x55,0xB7,0xB6,0xA2,0xF0,0x7A,0x29,0xF9,0xB9,0x4A,
+ 0x25,0x61,0x10,0x5F,0x7C,0xCE,0xA0,0x05,0x8F,0x3A,0x31,0xCB,0x14,0x7A,0xC7,0x27,
+ 0x04,0x53,0x19,0x42,0xAB,0x16,0x0B,0x13,0x5B,0x00,0x22,0x8B,0xF8,0x3B,0x78,0x7A,
+ 0xD7,0x75,0x82,0xF5,0x3E,0x29,0xA0,0x74,0x2C,0xA5,0xA8,0x88,0x59,0x44,0x61,0xFD,
+ 0x7E,0x10,0x40,0x1A,0x39,0xE1,0x2E,0xCB,0x49,0x95,0xFF,0x1E,0xED,0xDF,0xF6,0x5B,
+ 0x47,0x46,0x56,0xD5,0xA2,0x5A,0xAD,0x9D,0x51,0x27,0xEE,0xA4,0xEA,0x1D,0x04,0xF3,
+ 0x34,0xE7,0x25,0x2A,0x18,0x4E,0xDF,0x60,0x9A,0x64,0x01,0x54,0x76,0xB6,0x7A,0x68,
+ 0x78,0xC6,0x78,0xB2,0x98,0xA1,0x06,0xE4,0x15,0x77,0x78,0x0D,0xAF,0x86,0xCD,0xCD,
+ 0xB3,0xA7,0x2F,0x9C,0xD5,0x36,0xC3,0x1C,0xFC,0x42,0x14,0xEB,0x71,0x66,0x89,0x4D,
+ 0x18,0x51,0xE2,0xC7,0x97,0x05,0x7C,0x6E,0xB2,0x38,0xFF,0x7D,0xBD,0x11,0x6E,0x2E,
+ 0x0A,0x11,0x6B,0x2F,0x78,0x69,0x72,0x95,0x45,0xA3,0xD3,0xC7,0xBE,0xE6,0xCE,0x1E,
+ 0x4E,0xBC,0x40,0xC0,0xF2,0x33,0xAB,0xD0,0x79,0x10,0xDB,0x08,0x8C,0x4E,0xC8,0x26,
+ 0xE4,0x60,0x9A,0x2F,0x67,0x1F,0x13,0x00,0x27,0xEC,0x87,0x66,0xD8,0xF6,0x2B,0xC3,
+ 0xCB,0x48,0x5A,0x26,0x51,0x4D,0x29,0xF6,0x0D,0xB7,0x21,0xD7,0xEF,0x25,0xD9,0x9C,
+ 0xFF,0xE4,0xF9,0x54,0xA3,0xDD,0x75,0xEA,0x99,0x1C,0x76,0xFE,0x62,0x57,0xCF,0x29,
+ 0x96,0x97,0x1A,0x9B,0xAF,0xB9,0x1B,0x7E,0xB6,0xD7,0xCE,0x07,0xE6,0xAC,0x92,0x26,
+ 0xF7,0xDB,0xC5,0x2A,0xCF,0xDF,0x16,0x31,0x10,0x77,0x22,0xE3,0xC1,0x1E,0x70,0xFF,
+ 0x02,0x58,0x3B,0x35,0x9B,0x24,0x23,0x0A,0xA6,0xA2,0x0D,0x21,0xEB,0xC7,0xB9,0xC4,
+ 0xED,0x64,0x9B,0xCD,0xA8,0xF0,0x56,0x09,0xA4,0xC0,0x6D,0x31,0x22,0xE1,0x82,0x40,
+ 0x99,0xB7,0xAA,0x77,0x47,0xDF,0xCD,0x8A,0x51,0x1B,0xAF,0xC5,0x97,0x7D,0x16,0xC5,
+ 0x0B,0xDE,0x13,0x5B,0x95,0xBC,0x14,0x3C,0x5A,0x06,0x8A,0xF9,0x14,0xF3,0x12,0xB6,
+ 0x62,0x76,0x62,0xE6,0x4E,0x08,0x2F,0xBF,0xBF,0xBA,0x31,0xAA,0x32,0x2E,0x7E,0x69,
+ 0x5E,0xE6,0xAB,0xF1,0x6B,0xF0,0xB7,0x13,0x90,0x2F,0x2B,0xF3,0x98,0x2F,0xD6,0x7F,
+ 0xE0,0x4F,0x16,0x10,0x4D,0xB7,0xDE,0x00,0x82,0xD0,0x92,0x50,0xDC,0x3E,0xB9,0x63,
+ 0xAB,0xFA,0xC0,0xC1,0x64,0xC2,0x25,0xC9,0x45,0x84,0x4E,0x43,0xF0,0x1E,0xF5,0x06,
+ 0x06,0x51,0xB9,0x71,0xEE,0x52,0xE1,0x85,0xB7,0x01,0x87,0xAF,0xE3,0x6D,0x5F,0xC2,
+ 0x6A,0xB4,0x55,0xE7,0xAF,0x87,0xFD,0x30,0x92,0xB9,0x74,0xAB,0xFB,0x4C,0x16,0x95,
+ 0x23,0xA1,0xE4,0xF7,0x41,0x22,0x79,0xA8,0x93,0xE6,0x70,0x8D,0x02,0x20,0x85,0xCC,
+ 0x6A,0xFA,0x96,0x06,0x86,0x95,0xB3,0x6D,0x77,0x46,0xB8,0x62,0x48,0xBB,0x41,0x07,
+ 0xBC,0xD7,0xC7,0x8C,0x4B,0x84,0x37,0xC9,0x35,0x9D,0x71,0x6B,0x72,0xBD,0xD5,0x73,
+ 0x48,0x76,0x89,0x6F,0x7C,0x06,0x8C,0x99,0x66,0x05,0xA9,0x37,0x17,0xD7,0x27,0x5B,
+ 0x1F,0xC8,0x06,0x96,0xB3,0x9A,0xA3,0xC3,0x72,0x74,0xB8,0xC5,0x9D,0x23,0x56,0x7F,
+ 0x82,0xB6,0x67,0xD6,0xF7,0x81,0xED,0x33,0xD5,0x6B,0x91,0xDD,0xD9,0xAB,0x77,0x04,
+ 0xE7,0x57,0xFE,0x9D,0x36,0x0E,0x24,0x9B,0x8E,0x5C,0xEB,0xFF,0x04,0x88,0xB0,0xC8,
+ 0xCF,0x1F,0xA7,0x0A,0xB6,0x76,0x2F,0x8A,0x60,0x72,0x0D,0xFC,0x4E,0x06,0x59,0x89,
+ 0x0F,0x84,0x78,0x56,0x32,0xCB,0x59,0x1C,0x20,0xA7,0xD3,0xCB,0xB6,0xB7,0x58,0x94,
+ 0x35,0x1B,0xE2,0x89,0x46,0x48,0x38,0x1D,0x10,0x25,0x4F,0x88,0x45,0xAF,0x0E,0x00,
+ 0xBD,0x30,0xC4,0xC7,0x31,0x51,0xE3,0x68,0x5E,0xBA,0x66,0x84,0x2D,0x63,0x67,0xD6,
+ 0x35,0x3F,0xF5,0xA3,0xDF,0x94,0x59,0x8D,0xE7,0x80,0x22,0xD0,0xEA,0x7C,0xCF,0xCC,
+ 0xED,0x30,0x1B,0xED,0xDB,0x34,0xEE,0x3B,0x32,0xE8,0xEE,0x80,0x8C,0x96,0xF4,0x35,
+ 0xDC,0x55,0x8C,0x6D,0x32,0x04,0xAD,0x1A,0x01,0x45,0xB4,0x14,0x59,0x0E,0x70,0xAA,
+ 0x45,0xB3,0xFB,0x98,0x79,0xF3,0x7B,0x4A,0x12,0xCF,0x96,0x48,0x7A,0x03,0xB4,0xFE,
+ 0xDB,0xBA,0x82,0x62,0x7F,0x83,0xC5,0x72,0x51,0x01,0xC8,0x15,0xF3,0x0F,0x0C,0x68,
+ 0x28,0x98,0x9C,0x2B,0x95,0x29,0x29,0xF1,0xC0,0xB2,0x15,0x04,0x23,0xAC,0x81,0xBC,
+ 0x3F,0x8A,0x27,0xF5,0xA9,0xDB,0x30,0xAC,0xD3,0xE0,0x84,0x8A,0xE5,0x69,0x50,0xCE,
+ 0x16,0x43,0x54,0x4E,0xCA,0x4F,0xD5,0x7C,0x14,0x01,0xCA,0xB6,0x00,0x2B,0xEE,0x5C,
+ 0x0F,0x13,0x00,0x02,0x34,0x04,0x3D,0x60,0x25,0x4D,0x3D,0xBF,0x91,0x20,0x40,0x23,
+ 0xF0,0x09,0xC2,0x91,0xAA,0x8A,0x18,0x6C,0x81,0xF0,0x88,0xCC,0x56,0x66,0x89,0x2A,
+ 0xCC,0x19,0x2E,0xAE,0x07,0x3C,0x8B,0x6A,0x26,0x35,0xD5,0x20,0xCB,0xD8,0xE4,0xB5,
+ 0x8E,0xE6,0xFB,0x81,0xB6,0x1C,0x6A,0x11,0x29,0xFB,0x14,0x6A,0x1C,0x5F,0x44,0xD3,
+ 0x11,0xE7,0xA3,0x8A,0xA6,0x67,0x79,0xF3,0x19,0x4C,0x23,0x5B,0x52,0x73,0x6E,0x85,
+ 0xCF,0x01,0xFE,0xCC,0x79,0xF0,0x30,0x20,0x6C,0x78,0xE9,0xA7,0x5C,0x53,0xAE,0x4E,
+ 0x80,0x53,0x5D,0x60,0x5E,0x59,0x2B,0x07,0x95,0x74,0x4A,0x7A,0x26,0x6C,0x31,0x21,
+ 0x91,0x49,0x2C,0x64,0x63,0x62,0xCE,0x5F,0x72,0x60,0x6C,0x52,0xA4,0x97,0x70,0xB4,
+ 0x71,0x73,0x6F,0xFB,0xEF,0x8D,0x39,0x99,0xEE,0x73,0x69,0x97,0x8C,0x9E,0x57,0x07,
+ 0x19,0xE5,0x82,0x11,0x39,0x13,0x68,0xE1,0x9E,0x41,0xBB,0x5A,0xA6,0x86,0x50,0x33,
+ 0x6B,0xC0,0x22,0xA3,0x6F,0x90,0xD4,0x00,0x17,0x30,0x14,0x8D,0xDF,0x60,0x26,0xA0,
+ 0x3C,0x39,0xBB,0xF2,0x6B,0x66,0x0C,0x9F,0x67,0x1A,0xCB,0x73,0x84,0x09,0x9B,0x09,
+ 0x79,0xF9,0x19,0x86,0xF1,0x3B,0xCB,0x35,0x60,0xF0,0x0C,0xB8,0x78,0x2D,0x22,0x21,
+ 0x81,0xEC,0x27,0x44,0xF2,0x70,0xD6,0xD6,0xBA,0x74,0xE4,0xE6,0x81,0x70,0x5A,0xD6,
+ 0x1F,0x52,0x69,0x72,0x76,0x56,0xA4,0x5F,0xB6,0x1B,0x41,0x00,0x49,0x91,0xCD,0xF0,
+ 0x48,0xE4,0x3B,0x5F,0x00,0xF2,0x19,0x25,0x41,0x78,0xB0,0xC5,0x98,0x7C,0x58,0xD5,
+ 0xA5,0x32,0xD7,0xA0,0xC6,0x91,0x15,0xB9,0x68,0xF3,0x10,0x95,0x8F,0x30,0x4F,0xC9,
+ 0xEB,0xE1,0x37,0x55,0x1C,0x22,0x9B,0x59,0xD3,0x03,0xAC,0xBA,0x78,0x48,0xD2,0xDB,
+ 0x4C,0xB6,0x22,0x57,0xDF,0x88,0xDB,0x71,0xA9,0xC9,0xB1,0xFB,0x5D,0x4E,0xE4,0xE4,
+ 0x43,0xBD,0x3F,0xF3,0x55,0xE9,0x68,0x12,0xFE,0x4C,0xBE,0x8E,0xC3,0xB0,0xE2,0x80,
+ 0x58,0x12,0x62,0x8D,0xC3,0xA2,0x5B,0x38,0xDD,0x9D,0xD5,0x87,0x49,0x5D,0xF0,0xD1,
+ 0x68,0x51,0x27,0x60,0x30,0x10,0x12,0x70,0x5A,0x8A,0x7A,0x7C,0xEA,0xD7,0xA2,0xD3,
+ 0x01,0x01,0x80,0x21,0x21,0xF6,0x01,0x33,0xF8,0x66,0xAA,0x72,0xC2,0x3A,0xB8,0xFD,
+ 0x06,0xBF,0x00,0x1A,0x83,0x65,0xEB,0x3C,0x38,0xB1,0x75,0x36,0xDB,0x6B,0x02,0xD7,
+ 0xC5,0x3D,0xDD,0xCF,0x39,0xF0,0x0E,0x76,0xA7,0x3E,0x2A,0x9C,0xC6,0xB4,0x58,0x5E,
+ 0xE9,0xF0,0x49,0x77,0xD4,0xBC,0x61,0x05,0xC6,0x9F,0xD9,0x1D,0x1F,0xF5,0xE7,0x31,
+ 0x4C,0x78,0x8F,0x6A,0xB0,0x48,0x77,0xE7,0x83,0x8E,0x86,0xC5,0x41,0x5B,0x4B,0x81,
+ 0xBE,0xCB,0x4E,0x7E,0xC7,0x3C,0x20,0x5C,0x7A,0xBB,0x86,0x3F,0xD2,0x23,0x15,0x52,
+ 0x29,0xBA,0xC8,0xB6,0xFE,0x34,0x1E,0x84,0x2A,0x71,0xA9,0xA0,0x2D,0xF9,0xA4,0x1E,
+ 0xF1,0x52,0x69,0x54,0x44,0xFF,0xD7,0xE7,0xFB,0x00,0x22,0x34,0xF8,0xAC,0xD7,0x95,
+ 0x6E,0x1F,0xDD,0x17,0x6B,0xF3,0x41,0x16,0xB1,0x72,0x11,0xE0,0x8B,0xF5,0xCC,0xA3,
+ 0xBD,0x3E,0xF9,0x59,0x01,0x70,0x24,0x11,0x7F,0xED,0xF4,0x6C,0x17,0x6A,0x78,0xF3,
+ 0x1E,0xF6,0xAC,0xE7,0xF3,0x2D,0x54,0x16,0xDA,0x4D,0x61,0xB6,0xB0,0x2C,0x70,0xB8,
+ 0x71,0x78,0xEC,0x67,0x2E,0xD6,0x5B,0xA9,0xDE,0x7A,0x12,0xEF,0x62,0xE2,0xBB,0x8B,
+ 0x55,0xA9,0xA0,0x66,0xA3,0xA9,0x86,0x8E,0x61,0x73,0x75,0x74,0x36,0x40,0x85,0xFA,
+ 0x17,0xD2,0x09,0x28,0x94,0xB5,0x05,0xFE,0x00,0xBD,0x6C,0x4E,0x81,0xB7,0x00,0x39,
+ 0x25,0x38,0x69,0x97,0x45,0x29,0xC2,0xD3,0x61,0x7E,0xB7,0xB4,0x44,0xDF,0xBC,0x88,
+ 0xB4,0xC1,0x2F,0xB4,0x4B,0x4A,0xC9,0xD8,0x56,0x62,0xA1,0x1B,0xF4,0xEB,0x1D,0xD0,
+ 0xA0,0xAA,0xE1,0xCC,0x5F,0x3D,0x3B,0xDD,0x67,0xA1,0x17,0x1A,0x65,0x7C,0xC6,0xEC,
+ 0x9A,0x07,0xE4,0x1E,0xA4,0xAB,0x8D,0x9F,0xCD,0x8C,0x86,0x64,0xA8,0x7D,0x55,0xA3,
+ 0x2F,0x0D,0x1D,0x53,0x3A,0x10,0xCC,0x8B,0x84,0x0C,0xC4,0x2B,0x69,0x41,0x2F,0x12,
+ 0x80,0x00,0x00,0x00,0x00,0x00,0xFF,
+};
static const uint8_t uvd_decode_msg[] = {
0xe4,0x0d,0x00,0x00,0x01,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
@@ -341,6 +458,7 @@ static const uint8_t uvd_decode_msg[] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
+
static const uint8_t avc_decode_msg[] = {
0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x85,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -553,6 +671,218 @@ static const uint8_t avc_decode_msg[] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
+static const uint8_t hevc_decode_msg[] = {
+ 0x02,0x00,0x00,0x00,0x1e,0x00,0x00,0x00,0x85,0x00,0x00,0x00,0x88,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x01,0x00,0x03,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,
+ 0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
+
static const uint8_t uvd_destroy_msg[] = {
0xe4,0x0d,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -803,8 +1133,16 @@ static const uint8_t vcn_dec_create_msg[] = {
0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,
};
+static const uint8_t vcn_hevc_dec_create_msg[] = {
+ 0x28,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x28,0x00,0x00,0x00,
+ 0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x80,0x00,0x00,0x00,0x40,0x00,0x00,0x00,
+};
+
+
static const uint8_t vcn_dec_decode_msg[] = {
- 0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00,
0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00,
0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -821,17 +1159,50 @@ static const uint8_t vcn_dec_decode_msg[] = {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
+static const uint8_t vcn_hevc_dec_decode_msg[] = {
+ 0x28,0x00,0x00,0x00,0xe0,0x01,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+ 0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x58,0x00,0x00,0x00,
+ 0xbc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x14,0x01,0x00,0x00,
+ 0xa8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x80,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x80,0x07,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0b,0x02,0x00,
+ 0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
+ 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
+
static const uint8_t vcn_dec_destroy_msg[] = {
0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,
0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
};
+static const uint8_t vcn_hevc_dec_destroy_msg[] = {
+ 0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,
+ 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,
+};
+
static const uint8_t feedback_msg[] = {
0x2c,0x00,0x00,0x00,0x2c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
+static const uint8_t hevc_feedback_msg[] = {
+ 0x2c,0x00,0x00,0x00,0x2c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
+
static const uint8_t jpeg_bitstream[] = {
0xFF, 0xD8, 0xFF, 0xDB, 0x01, 0x06, 0x00, 0x08, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05,
0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
diff --git a/lib/amdgpu/amd_mmd_frame.h b/lib/amdgpu/amd_mmd_frame.h
index e3141466d..774f11547 100644
--- a/lib/amdgpu/amd_mmd_frame.h
+++ b/lib/amdgpu/amd_mmd_frame.h
@@ -1928,4 +1928,775 @@ static const uint8_t frame[] = {
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
};
+
+static const char frame_128_64[] = {
+ 0x65, 0x64, 0x5f, 0x62, 0x70, 0x7c, 0x7d, 0x7c, 0x7d, 0x79, 0x73, 0x72, 0x76, 0x75, 0x77,0x7f,
+ 0x83, 0x84, 0x81, 0x80, 0x7f, 0x80, 0x82, 0x83, 0x8d, 0x93, 0x93, 0x92, 0x97, 0x98, 0x94,0x90,
+ 0x89, 0x85, 0x80, 0x7b, 0x75, 0x70, 0x6e, 0x6c, 0x6a, 0x69, 0x69, 0x69, 0x68, 0x68, 0x68,0x69,
+ 0x6f, 0x77, 0x84, 0x87, 0x97, 0x87, 0x6d, 0x6f, 0x79, 0x6d, 0x5d, 0x54, 0x56, 0x60, 0x6c,0x71,
+ 0x69, 0x5b, 0x53, 0x55, 0x58, 0x58, 0x58, 0x58, 0x5c, 0x61, 0x63, 0x64, 0x64, 0x65, 0x60,0x5b,
+ 0x5e, 0x5f, 0x5f, 0x61, 0x64, 0x64, 0x61, 0x5e, 0x5b, 0x59, 0x56, 0x54, 0x53, 0x54, 0x55,0x57,
+ 0x55, 0x52, 0x4d, 0x48, 0x45, 0x44, 0x46, 0x47, 0x4a, 0x4f, 0x54, 0x51, 0x49, 0x40, 0x3c,0x3c,
+ 0x3c, 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x39, 0x38, 0x2e, 0x2e, 0x31, 0x35, 0x34, 0x34, 0x45,0x5d,
+ 0x69, 0x67, 0x63, 0x66, 0x74, 0x7f, 0x81, 0x7f, 0x80, 0x7b, 0x74, 0x74, 0x76, 0x76, 0x76,0x7d,
+ 0x84, 0x85, 0x85, 0x83, 0x83, 0x83, 0x84, 0x84, 0x8e, 0x94, 0x94, 0x92, 0x96, 0x96, 0x93,0x8f,
+ 0x8e, 0x8b, 0x89, 0x85, 0x80, 0x7c, 0x78, 0x76, 0x76, 0x75, 0x74, 0x73, 0x73, 0x72, 0x71,0x71,
+ 0x78, 0x7c, 0x83, 0x90, 0x86, 0x82, 0x6d, 0x64, 0x74, 0x69, 0x5c, 0x53, 0x51, 0x57, 0x5e,0x62,
+ 0x5f, 0x57, 0x50, 0x52, 0x55, 0x56, 0x55, 0x55, 0x5a, 0x60, 0x64, 0x64, 0x62, 0x61, 0x5d,0x5a,
+ 0x5d, 0x5d, 0x5d, 0x5f, 0x62, 0x62, 0x5f, 0x5d, 0x5b, 0x59, 0x56, 0x53, 0x52, 0x51, 0x51,0x52,
+ 0x50, 0x4d, 0x48, 0x44, 0x41, 0x40, 0x42, 0x44, 0x48, 0x4d, 0x50, 0x4d, 0x44, 0x3c, 0x39,0x3a,
+ 0x3a, 0x39, 0x39, 0x39, 0x39, 0x39, 0x38, 0x38, 0x2f, 0x32, 0x31, 0x3d, 0x44, 0x46, 0x55,0x66,
+ 0x6c, 0x6a, 0x66, 0x68, 0x76, 0x82, 0x85, 0x83, 0x83, 0x7e, 0x77, 0x76, 0x79, 0x78, 0x77,0x7c,
+ 0x85, 0x86, 0x87, 0x87, 0x86, 0x85, 0x83, 0x82, 0x8e, 0x95, 0x95, 0x91, 0x93, 0x93, 0x8f,0x8f,
+ 0x90, 0x93, 0x94, 0x94, 0x91, 0x8d, 0x8a, 0x87, 0x86, 0x86, 0x86, 0x85, 0x85, 0x83, 0x82,0x81,
+ 0x8a, 0x84, 0x8f, 0x92, 0x7f, 0x74, 0x73, 0x62, 0x65, 0x5e, 0x57, 0x55, 0x55, 0x57, 0x58,0x5a,
+ 0x58, 0x56, 0x4f, 0x50, 0x53, 0x53, 0x53, 0x54, 0x5a, 0x63, 0x63, 0x5e, 0x5e, 0x5e, 0x5c,0x5c,
+ 0x5c, 0x5b, 0x5b, 0x5c, 0x5e, 0x5e, 0x5c, 0x5a, 0x59, 0x58, 0x55, 0x52, 0x4e, 0x4d, 0x4d,0x4d,
+ 0x4b, 0x49, 0x45, 0x41, 0x3f, 0x40, 0x42, 0x44, 0x48, 0x4d, 0x50, 0x4b, 0x42, 0x3b, 0x38,0x39,
+ 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x38, 0x38, 0x30, 0x37, 0x3b, 0x45, 0x4a, 0x4c, 0x5c,0x6d,
+ 0x6e, 0x6c, 0x67, 0x69, 0x77, 0x85, 0x87, 0x87, 0x87, 0x82, 0x7c, 0x7d, 0x81, 0x7f, 0x7d,0x81,
+ 0x85, 0x88, 0x88, 0x89, 0x89, 0x87, 0x83, 0x81, 0x8f, 0x96, 0x95, 0x8f, 0x8f, 0x8e, 0x8b,0x8e,
+ 0x93, 0x98, 0x9c, 0x9f, 0x9e, 0x9b, 0x98, 0x95, 0x95, 0x95, 0x96, 0x97, 0x96, 0x94, 0x92,0x90,
+ 0x8f, 0x8e, 0x9a, 0x9a, 0x8b, 0x71, 0x73, 0x68, 0x59, 0x57, 0x56, 0x58, 0x5a, 0x5c, 0x59,0x59,
+ 0x56, 0x54, 0x4d, 0x4e, 0x4e, 0x4d, 0x4e, 0x50, 0x5a, 0x62, 0x62, 0x5f, 0x5e, 0x60, 0x5f,0x5c,
+ 0x5a, 0x58, 0x58, 0x59, 0x5b, 0x5a, 0x58, 0x55, 0x53, 0x54, 0x51, 0x4f, 0x4d, 0x4b, 0x4a,0x4a,
+ 0x48, 0x47, 0x43, 0x40, 0x3f, 0x41, 0x44, 0x48, 0x4c, 0x51, 0x50, 0x4b, 0x41, 0x3a, 0x38,0x39,
+ 0x39, 0x39, 0x38, 0x39, 0x3a, 0x3a, 0x38, 0x38, 0x37, 0x3d, 0x46, 0x3f, 0x37, 0x45, 0x5f,0x6e,
+ 0x71, 0x6f, 0x6a, 0x6b, 0x79, 0x86, 0x8a, 0x8b, 0x8c, 0x87, 0x82, 0x85, 0x8b, 0x8a, 0x88,0x87,
+ 0x88, 0x89, 0x8a, 0x8a, 0x8a, 0x88, 0x86, 0x83, 0x90, 0x97, 0x95, 0x8d, 0x8a, 0x88, 0x86,0x8a,
+ 0x93, 0x9c, 0xa0, 0xa3, 0xa5, 0xa4, 0xa1, 0x9f, 0xa0, 0xa2, 0xa2, 0xa3, 0xa1, 0x9d, 0x9a,0x97,
+ 0x8a, 0x92, 0x93, 0xa0, 0x95, 0x7d, 0x69, 0x69, 0x61, 0x5e, 0x5a, 0x5a, 0x5c, 0x5c, 0x5a,0x59,
+ 0x55, 0x52, 0x4c, 0x4a, 0x49, 0x46, 0x45, 0x47, 0x56, 0x58, 0x61, 0x68, 0x67, 0x6b, 0x66,0x56,
+ 0x58, 0x57, 0x56, 0x57, 0x58, 0x57, 0x53, 0x50, 0x4e, 0x4e, 0x4e, 0x4d, 0x4b, 0x4a, 0x49,0x48,
+ 0x47, 0x45, 0x42, 0x40, 0x3f, 0x42, 0x44, 0x48, 0x4f, 0x51, 0x50, 0x49, 0x3e, 0x38, 0x38,0x39,
+ 0x3a, 0x39, 0x38, 0x38, 0x40, 0x3a, 0x39, 0x42, 0x4d, 0x44, 0x4a, 0x36, 0x2f, 0x4f, 0x5f,0x59,
+ 0x78, 0x75, 0x70, 0x71, 0x7d, 0x89, 0x8d, 0x8f, 0x90, 0x8c, 0x89, 0x8d, 0x92, 0x94, 0x91,0x8f,
+ 0x8d, 0x8c, 0x8b, 0x8c, 0x8d, 0x8d, 0x8c, 0x8a, 0x93, 0x98, 0x95, 0x8b, 0x86, 0x84, 0x82,0x87,
+ 0x93, 0x9e, 0xa3, 0xa5, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa9, 0xaa, 0xa9, 0xa6, 0xa0, 0x9b,0x98,
+ 0x95, 0x94, 0x8a, 0x8f, 0x96, 0x85, 0x70, 0x70, 0x67, 0x60, 0x5b, 0x58, 0x59, 0x5a, 0x5a,0x58,
+ 0x54, 0x50, 0x4b, 0x4a, 0x47, 0x44, 0x44, 0x47, 0x4e, 0x55, 0x5b, 0x62, 0x6d, 0x70, 0x67,0x5c,
+ 0x58, 0x57, 0x56, 0x56, 0x57, 0x56, 0x51, 0x4d, 0x4a, 0x4a, 0x4a, 0x4b, 0x4a, 0x49, 0x48,0x47,
+ 0x45, 0x42, 0x3f, 0x3d, 0x3d, 0x3f, 0x43, 0x47, 0x4e, 0x4f, 0x4c, 0x44, 0x3a, 0x35, 0x37,0x3a,
+ 0x3a, 0x37, 0x35, 0x35, 0x3c, 0x36, 0x3e, 0x54, 0x62, 0x51, 0x54, 0x4e, 0x52, 0x6b, 0x5d,0x37,
+ 0x81, 0x7e, 0x79, 0x79, 0x82, 0x8c, 0x90, 0x91, 0x93, 0x90, 0x8e, 0x90, 0x96, 0x97, 0x95,0x92,
+ 0x91, 0x90, 0x8e, 0x8f, 0x91, 0x93, 0x95, 0x94, 0x97, 0x9a, 0x96, 0x8a, 0x84, 0x7f, 0x7f,0x84,
+ 0x95, 0x9e, 0xa3, 0xa6, 0xa7, 0xa8, 0xa9, 0xab, 0xac, 0xad, 0xad, 0xac, 0xa7, 0xa0, 0x99,0x96,
+ 0x97, 0x8c, 0x8b, 0x7c, 0x83, 0x7f, 0x79, 0x70, 0x5c, 0x5d, 0x5f, 0x63, 0x66, 0x65, 0x60,0x59,
+ 0x52, 0x4e, 0x4b, 0x4a, 0x48, 0x46, 0x48, 0x4d, 0x4d, 0x52, 0x4f, 0x56, 0x6a, 0x6e, 0x67,0x65,
+ 0x59, 0x57, 0x56, 0x56, 0x57, 0x55, 0x50, 0x4c, 0x49, 0x49, 0x49, 0x49, 0x48, 0x46, 0x43,0x40,
+ 0x3f, 0x3d, 0x3a, 0x3a, 0x3a, 0x3d, 0x41, 0x44, 0x48, 0x4a, 0x47, 0x3e, 0x35, 0x32, 0x36,0x3a,
+ 0x39, 0x34, 0x32, 0x31, 0x37, 0x37, 0x49, 0x61, 0x65, 0x64, 0x68, 0x6b, 0x6b, 0x6b, 0x52,0x2a,
+ 0x85, 0x82, 0x7e, 0x7e, 0x85, 0x8d, 0x91, 0x93, 0x93, 0x90, 0x8e, 0x8f, 0x94, 0x95, 0x92,0x91,
+ 0x91, 0x92, 0x91, 0x93, 0x94, 0x95, 0x99, 0x9a, 0x9b, 0x9c, 0x97, 0x8a, 0x83, 0x7f, 0x7c,0x84,
+ 0x97, 0x9e, 0xa4, 0xa6, 0xa8, 0xa9, 0xab, 0xae, 0xb1, 0xb1, 0xad, 0xab, 0xa8, 0xa0, 0x98,0x93,
+ 0x85, 0x81, 0x8a, 0x7e, 0x6a, 0x79, 0x73, 0x62, 0x5e, 0x66, 0x74, 0x80, 0x83, 0x7c, 0x6e,0x61,
+ 0x52, 0x4e, 0x4b, 0x4b, 0x4b, 0x4a, 0x4e, 0x54, 0x4f, 0x49, 0x4e, 0x55, 0x5c, 0x69, 0x6d,0x64,
+ 0x59, 0x57, 0x56, 0x56, 0x57, 0x54, 0x4f, 0x4b, 0x48, 0x48, 0x48, 0x47, 0x45, 0x41, 0x3e,0x3b,
+ 0x3a, 0x3b, 0x39, 0x38, 0x38, 0x3c, 0x3f, 0x42, 0x44, 0x46, 0x43, 0x3b, 0x33, 0x30, 0x35,0x39,
+ 0x36, 0x33, 0x2f, 0x2d, 0x37, 0x42, 0x53, 0x61, 0x66, 0x73, 0x6d, 0x6b, 0x5e, 0x4a, 0x45,0x32,
+ 0x82, 0x7f, 0x7d, 0x7d, 0x83, 0x89, 0x8c, 0x8e, 0x90, 0x8d, 0x8a, 0x8b, 0x8f, 0x90, 0x8f,0x8e,
+ 0x90, 0x91, 0x93, 0x94, 0x94, 0x97, 0x9a, 0x9d, 0xa2, 0xa1, 0x99, 0x8e, 0x83, 0x7c, 0x7b,0x85,
+ 0x9a, 0x9c, 0xa2, 0xa5, 0xa7, 0xa9, 0xac, 0xb1, 0xb4, 0xb4, 0xad, 0xa9, 0xa8, 0x9c, 0x8e,0x8e,
+ 0x78, 0x70, 0x79, 0x7c, 0x76, 0x73, 0x6e, 0x64, 0x72, 0x8a, 0x98, 0x96, 0x89, 0x80, 0x77,0x70,
+ 0x65, 0x65, 0x65, 0x63, 0x60, 0x60, 0x64, 0x66, 0x5a, 0x4f, 0x49, 0x45, 0x57, 0x57, 0x6d,0x68,
+ 0x56, 0x55, 0x51, 0x4c, 0x54, 0x50, 0x4b, 0x48, 0x47, 0x46, 0x43, 0x42, 0x3f, 0x3d, 0x3a,0x38,
+ 0x37, 0x38, 0x39, 0x36, 0x38, 0x3c, 0x3e, 0x3f, 0x42, 0x44, 0x40, 0x3a, 0x33, 0x30, 0x34,0x37,
+ 0x31, 0x31, 0x2f, 0x2d, 0x3e, 0x51, 0x54, 0x63, 0x73, 0x65, 0x52, 0x3f, 0x2c, 0x3d, 0x49,0x28,
+ 0x79, 0x77, 0x75, 0x75, 0x7a, 0x7f, 0x82, 0x84, 0x87, 0x85, 0x83, 0x83, 0x87, 0x89, 0x89,0x89,
+ 0x8b, 0x8e, 0x92, 0x92, 0x91, 0x93, 0x97, 0x9b, 0x9e, 0x9a, 0x8f, 0x83, 0x7b, 0x76, 0x7b,0x8a,
+ 0x98, 0x9b, 0x9f, 0xa3, 0xa6, 0xa7, 0xab, 0xb2, 0xb7, 0xb7, 0xad, 0xa7, 0xa5, 0x96, 0x87,0x88,
+ 0x88, 0x82, 0x7f, 0x76, 0x6e, 0x69, 0x71, 0x80, 0x92, 0x9c, 0x9e, 0x94, 0x88, 0x82, 0x81,0x81,
+ 0x80, 0x80, 0x80, 0x7c, 0x78, 0x75, 0x76, 0x77, 0x6d, 0x59, 0x4a, 0x42, 0x44, 0x51, 0x60,0x62,
+ 0x5b, 0x5b, 0x51, 0x45, 0x4f, 0x49, 0x44, 0x44, 0x43, 0x40, 0x3f, 0x3d, 0x3b, 0x3a, 0x38,0x37,
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+ 0x7f, 0x91, 0x80, 0x91, 0x7d, 0x94, 0x7c, 0x95, 0x8d, 0x7f, 0x91, 0x77, 0x8f, 0x88, 0x8e,0x84,
+ 0x85, 0x84, 0x7d, 0x86, 0x7c, 0x86, 0x82, 0x7f, 0x88, 0x79, 0x8a, 0x78, 0x8c, 0x76, 0x8f,0x73,
+ 0x90, 0x77, 0x8f, 0x83, 0x95, 0x98, 0x9a, 0x9d, 0x9c, 0xa1, 0x9f, 0xa3, 0xa0, 0x98, 0x9b,0x8d,
+ 0x93, 0x87, 0x91, 0x82, 0x95, 0x7d, 0x95, 0x7a, 0x97, 0x77, 0x99, 0x78, 0x93, 0x86, 0x93,0x93,
+ 0x7b, 0x88, 0x7d, 0x87, 0x7d, 0x83, 0x7d, 0x7d, 0x7f, 0x85, 0x7f, 0x85, 0x7f, 0x85, 0x7f,0x87,
+ 0x7f, 0x87, 0x7f, 0x89, 0x7f, 0x89, 0x7f, 0x89, 0x81, 0x82, 0x7c, 0x7e, 0x73, 0x77, 0x71,0x70,
+ 0x78, 0x65, 0x93, 0x63, 0x98, 0x61, 0x8d, 0x73, 0x94, 0x73, 0x94, 0x54, 0x8b, 0x67, 0x87,0x7d,
+ 0x84, 0x84, 0x83, 0x86, 0x7f, 0x86, 0x7c, 0x86, 0x7b, 0x8b, 0x7b, 0x8d, 0x7b, 0x90, 0x7c,0x90,
+ 0x7c, 0x8f, 0x7d, 0x8f, 0x7b, 0x90, 0x79, 0x90, 0x85, 0x80, 0x89, 0x7a, 0x88, 0x88, 0x86,0x82,
+ 0x82, 0x81, 0x7f, 0x85, 0x81, 0x87, 0x88, 0x82, 0x86, 0x7e, 0x87, 0x7c, 0x88, 0x79, 0x89,0x75,
+ 0x8a, 0x78, 0x8c, 0x87, 0x96, 0x98, 0x99, 0x9b, 0x9c, 0x9d, 0x9c, 0xa3, 0x9e, 0x9a, 0x98,0x89,
+ 0x8a, 0x80, 0x87, 0x7b, 0x8c, 0x75, 0x8c, 0x73, 0x8c, 0x72, 0x8d, 0x76, 0x86, 0x86, 0x8a,0x96,
+ 0x7d, 0x8a, 0x7d, 0x83, 0x7d, 0x7f, 0x7d, 0x81, 0x7f, 0x81, 0x7f, 0x81, 0x7f, 0x81, 0x7f,0x83,
+ 0x7f, 0x83, 0x7f, 0x85, 0x7f, 0x85, 0x7f, 0x85, 0x80, 0x80, 0x7b, 0x7c, 0x72, 0x77, 0x6c,0x71,
+ 0x6f, 0x6c, 0x7f, 0x64, 0x84, 0x63, 0x81, 0x7e, 0x8c, 0x74, 0x8c, 0x54, 0x88, 0x71, 0x84,0x75,
+ 0x82, 0x84, 0x7f, 0x86, 0x7b, 0x86, 0x78, 0x86, 0x78, 0x89, 0x79, 0x8c, 0x79, 0x8e, 0x79,0x8d,
+ 0x79, 0x8e, 0x79, 0x8b, 0x76, 0x89, 0x76, 0x87, 0x7b, 0x84, 0x7d, 0x7d, 0x7d, 0x88, 0x7c,0x81,
+ 0x77, 0x7c, 0x7a, 0x83, 0x81, 0x89, 0x8a, 0x87, 0x82, 0x83, 0x83, 0x80, 0x84, 0x7d, 0x83,0x78,
+ 0x7f, 0x7b, 0x84, 0x8a, 0x94, 0x9c, 0x99, 0xa0, 0x9c, 0xa0, 0x98, 0xa3, 0x9a, 0x9d, 0x95,0x8f,
+ 0x88, 0x8d, 0x87, 0x8c, 0x8c, 0x89, 0x8c, 0x8a, 0x8a, 0x8a, 0x8b, 0x88, 0x82, 0x91, 0x87,0x9f,
+ 0x7d, 0x8d, 0x7d, 0x81, 0x7d, 0x7d, 0x7d, 0x81, 0x7f, 0x7e, 0x7f, 0x7e, 0x7f, 0x7e, 0x7f,0x80,
+ 0x7f, 0x80, 0x7f, 0x82, 0x7f, 0x82, 0x7f, 0x82, 0x7e, 0x84, 0x7e, 0x83, 0x7c, 0x7e, 0x79,0x79,
+ 0x74, 0x76, 0x6e, 0x72, 0x71, 0x69, 0x7f, 0x76, 0x88, 0x66, 0x88, 0x62, 0x85, 0x72, 0x83,0x6e,
+ 0x80, 0x84, 0x7c, 0x86, 0x78, 0x86, 0x77, 0x86, 0x77, 0x88, 0x77, 0x8a, 0x78, 0x8c, 0x78,0x8d,
+ 0x78, 0x8d, 0x76, 0x89, 0x74, 0x84, 0x74, 0x81, 0x74, 0x86, 0x75, 0x7f, 0x75, 0x88, 0x74,0x7f,
+ 0x69, 0x77, 0x6f, 0x81, 0x7c, 0x8a, 0x84, 0x8a, 0x7b, 0x87, 0x7d, 0x84, 0x7e, 0x81, 0x7e,0x7d,
+ 0x77, 0x80, 0x7e, 0x8d, 0x91, 0x9d, 0x9a, 0xa4, 0x9e, 0xa3, 0x97, 0xa3, 0x98, 0x9d, 0x94,0x98,
+ 0x8b, 0xa0, 0x8e, 0xa2, 0x94, 0x9d, 0x93, 0x9f, 0x91, 0x9d, 0x92, 0x96, 0x87, 0x98, 0x8b,0xa3,
+};
#endif //_AMD_MMD_FRAME_H_
diff --git a/tests/amdgpu/amd_vcn.c b/tests/amdgpu/amd_vcn.c
index bd8c9da23..6a8831b11 100644
--- a/tests/amdgpu/amd_vcn.c
+++ b/tests/amdgpu/amd_vcn.c
@@ -1,32 +1,11 @@
-// SPDX-License-Identifier: MIT
/*
* Copyright 2023 Advanced Micro Devices, Inc.
* Copyright 2014 Advanced Micro Devices, Inc.
*/
#include "lib/amdgpu/amd_mmd_shared.h"
-
-#define DECODE_CMD_MSG_BUFFER 0x00000000
-#define DECODE_CMD_DPB_BUFFER 0x00000001
-#define DECODE_CMD_DECODING_TARGET_BUFFER 0x00000002
-#define DECODE_CMD_FEEDBACK_BUFFER 0x00000003
-#define DECODE_CMD_PROB_TBL_BUFFER 0x00000004
-#define DECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005
-#define DECODE_CMD_BITSTREAM_BUFFER 0x00000100
-#define DECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204
-#define DECODE_CMD_CONTEXT_BUFFER 0x00000206
-
-#define DECODE_IB_PARAM_DECODE_BUFFER (0x00000001)
-
-#define DECODE_CMDBUF_FLAGS_MSG_BUFFER (0x00000001)
-#define DECODE_CMDBUF_FLAGS_DPB_BUFFER (0x00000002)
-#define DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER (0x00000004)
-#define DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER (0x00000008)
-#define DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER (0x00000010)
-#define DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER (0x00000200)
-#define DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER (0x00000800)
-#define DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER (0x00001000)
-#define DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER (0x00100000)
+#include "amd_vcn_common.h"
+#include "amd_vcn_hevc.h"
#define H264_NAL_TYPE_NON_IDR_SLICE 1
#define H264_NAL_TYPE_DP_A_SLICE 2
@@ -42,469 +21,6 @@
#define H264_NAL_TYPE_FILLER_DATA 0xc
#define H264_NAL_TYPE_SEQ_EXTENSION 0xd
-#define H264_START_CODE 0x000001
-
-
-struct rvcn_decode_buffer {
- unsigned int valid_buf_flag;
- unsigned int msg_buffer_address_hi;
- unsigned int msg_buffer_address_lo;
- unsigned int dpb_buffer_address_hi;
- unsigned int dpb_buffer_address_lo;
- unsigned int target_buffer_address_hi;
- unsigned int target_buffer_address_lo;
- unsigned int session_contex_buffer_address_hi;
- unsigned int session_contex_buffer_address_lo;
- unsigned int bitstream_buffer_address_hi;
- unsigned int bitstream_buffer_address_lo;
- unsigned int context_buffer_address_hi;
- unsigned int context_buffer_address_lo;
- unsigned int feedback_buffer_address_hi;
- unsigned int feedback_buffer_address_lo;
- unsigned int luma_hist_buffer_address_hi;
- unsigned int luma_hist_buffer_address_lo;
- unsigned int prob_tbl_buffer_address_hi;
- unsigned int prob_tbl_buffer_address_lo;
- unsigned int sclr_coeff_buffer_address_hi;
- unsigned int sclr_coeff_buffer_address_lo;
- unsigned int it_sclr_table_buffer_address_hi;
- unsigned int it_sclr_table_buffer_address_lo;
- unsigned int sclr_target_buffer_address_hi;
- unsigned int sclr_target_buffer_address_lo;
- unsigned int cenc_size_info_buffer_address_hi;
- unsigned int cenc_size_info_buffer_address_lo;
- unsigned int mpeg2_pic_param_buffer_address_hi;
- unsigned int mpeg2_pic_param_buffer_address_lo;
- unsigned int mpeg2_mb_control_buffer_address_hi;
- unsigned int mpeg2_mb_control_buffer_address_lo;
- unsigned int mpeg2_idct_coeff_buffer_address_hi;
- unsigned int mpeg2_idct_coeff_buffer_address_lo;
-};
-
-struct rvcn_decode_ib_package {
- unsigned int package_size;
- unsigned int package_type;
-};
-
-
-struct amdgpu_vcn_reg {
- uint32_t data0;
- uint32_t data1;
- uint32_t cmd;
- uint32_t nop;
- uint32_t cntl;
-};
-
-struct buffer_info {
- uint32_t num_bits_in_buffer;
- const uint8_t *dec_buffer;
- uint8_t dec_data;
- uint32_t dec_buffer_size;
- const uint8_t *end;
-};
-
-struct h264_decode {
- uint8_t profile;
- uint8_t level_idc;
- uint8_t nal_ref_idc;
- uint8_t nal_unit_type;
- uint32_t pic_width, pic_height;
- uint32_t slice_type;
-};
-
-struct vcn_context {
- struct amdgpu_mmd_bo enc_buf;
- struct amdgpu_mmd_bo cpb_buf;
- struct amdgpu_mmd_bo session_ctx_buf;
- uint32_t enc_task_id;
- uint32_t *ib_checksum;
- uint32_t *ib_size_in_dw;
- uint32_t gWidth, gHeight, gSliceType;
- struct rvcn_decode_buffer *decode_buffer;
-};
-
-static struct amdgpu_vcn_reg reg[] = {
- {0x81c4, 0x81c5, 0x81c3, 0x81ff, 0x81c6},
- {0x504, 0x505, 0x503, 0x53f, 0x506},
- {0x10, 0x11, 0xf, 0x29, 0x26d},
-};
-
-static uint32_t
-bs_read_u(struct buffer_info *buf_info, int n);
-
-static uint32_t
-bs_read_ue(struct buffer_info *buf_info);
-
-static bool
-is_vcn_tests_enable(amdgpu_device_handle device_handle, struct mmd_context *context)
-{
- struct drm_amdgpu_info_hw_ip info;
- int r;
-
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_ENC, 0, &info);
-
- if (r)
- return false;
-
- context->vcn_ip_version_major = info.hw_ip_version_major;
- context->vcn_ip_version_minor = info.hw_ip_version_minor;
- context->enc_ring = !!info.available_rings;
- /* in vcn 4.0 it re-uses encoding queue as unified queue */
- if (context->vcn_ip_version_major >= 4) {
- context->vcn_unified_ring = true;
- context->vcn_dec_sw_ring = true;
- context->dec_ring = context->enc_ring;
- } else {
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
- context->dec_ring = !!info.available_rings;
- }
-
- if (!(context->dec_ring || context->enc_ring) ||
- (context->family_id < AMDGPU_FAMILY_RV &&
- (context->family_id == AMDGPU_FAMILY_AI &&
- (context->chip_id - context->chip_rev) < 0x32))) { /* Arcturus */
- igt_info("The ASIC does NOT support VCN, vcn test is disabled\n");
- return false;
- }
-
- if (context->family_id == AMDGPU_FAMILY_AI)
- context->enc_ring = false;
-
- if (!context->dec_ring) {
- igt_info("VCN Tests DEC create disable");
- igt_info("VCN Tests DEC decode disable");
- igt_info("VCN Tests DEC destroy disable");
- }
-
- if (!context->enc_ring) {
- igt_info("VCN Tests ENC create disable");
- igt_info("VCN Tests ENC encode disable");
- igt_info("VCN Tests ENC destroy disable");
- }
-
- if (context->vcn_ip_version_major == 1) {
- context->vcn_reg_index = 0;
- } else if (context->vcn_ip_version_major == 2 && context->vcn_ip_version_minor == 0) {
- context->vcn_reg_index = 1;
- } else if ((context->vcn_ip_version_major == 2 && context->vcn_ip_version_minor >= 5) ||
- context->vcn_ip_version_major == 3) {
- context->vcn_reg_index = 2;
- }
-
- return true;
-}
-
-static void
-amdgpu_cs_sq_head(struct vcn_context *v_context, uint32_t *base, int *offset, bool enc)
-{
- /* signature */
- *(base + (*offset)++) = 0x00000010;
- *(base + (*offset)++) = 0x30000002;
- v_context->ib_checksum = base + (*offset)++;
- v_context->ib_size_in_dw = base + (*offset)++;
-
- /* engine info */
- *(base + (*offset)++) = 0x00000010;
- *(base + (*offset)++) = 0x30000001;
- *(base + (*offset)++) = enc ? 2 : 3;
- *(base + (*offset)++) = 0x00000000;
-}
-
-static void
-amdgpu_cs_sq_ib_tail(struct vcn_context *v_context, uint32_t *end)
-{
- uint32_t size_in_dw;
- uint32_t checksum = 0;
-
- /* if the pointers are invalid, no need to process */
- if (v_context->ib_checksum == NULL || v_context->ib_size_in_dw == NULL)
- return;
-
- size_in_dw = end - v_context->ib_size_in_dw - 1;
- *v_context->ib_size_in_dw = size_in_dw;
- *(v_context->ib_size_in_dw + 4) = size_in_dw * sizeof(uint32_t);
-
- for (int i = 0; i < size_in_dw; i++)
- checksum += *(v_context->ib_checksum + 2 + i);
-
- *v_context->ib_checksum = checksum;
-
- v_context->ib_checksum = NULL;
- v_context->ib_size_in_dw = NULL;
-}
-
-static void
-vcn_dec_cmd(struct mmd_context *context, struct vcn_context *v_context,
- uint64_t addr, unsigned int cmd, int *idx)
-{
- if (context->vcn_dec_sw_ring == false) {
- context->ib_cpu[(*idx)++] = reg[context->vcn_reg_index].data0;
- context->ib_cpu[(*idx)++] = addr;
- context->ib_cpu[(*idx)++] = reg[context->vcn_reg_index].data1;
- context->ib_cpu[(*idx)++] = addr >> 32;
- context->ib_cpu[(*idx)++] = reg[context->vcn_reg_index].cmd;
- context->ib_cpu[(*idx)++] = cmd << 1;
- return;
- }
-
- /* Support decode software ring message */
- if (!(*idx)) {
- struct rvcn_decode_ib_package *ib_header;
-
- if (context->vcn_unified_ring)
- amdgpu_cs_sq_head(v_context, context->ib_cpu, idx, false);
-
- ib_header = (struct rvcn_decode_ib_package *)&context->ib_cpu[*idx];
- ib_header->package_size = sizeof(struct rvcn_decode_buffer) +
- sizeof(struct rvcn_decode_ib_package);
-
- (*idx)++;
- ib_header->package_type = (DECODE_IB_PARAM_DECODE_BUFFER);
- (*idx)++;
-
- v_context->decode_buffer = (struct rvcn_decode_buffer *)&(context->ib_cpu[*idx]);
- *idx += sizeof(struct rvcn_decode_buffer) / 4;
- memset(v_context->decode_buffer, 0, sizeof(struct rvcn_decode_buffer));
- }
-
- switch (cmd) {
- case DECODE_CMD_MSG_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= DECODE_CMDBUF_FLAGS_MSG_BUFFER;
- v_context->decode_buffer->msg_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->msg_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_DPB_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DPB_BUFFER);
- v_context->decode_buffer->dpb_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->dpb_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_DECODING_TARGET_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER);
- v_context->decode_buffer->target_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->target_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_FEEDBACK_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER);
- v_context->decode_buffer->feedback_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->feedback_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_PROB_TBL_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER);
- v_context->decode_buffer->prob_tbl_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->prob_tbl_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_SESSION_CONTEXT_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER);
- v_context->decode_buffer->session_contex_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->session_contex_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_BITSTREAM_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER);
- v_context->decode_buffer->bitstream_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->bitstream_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_IT_SCALING_TABLE_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER);
- v_context->decode_buffer->it_sclr_table_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->it_sclr_table_buffer_address_lo = (addr);
- break;
- case DECODE_CMD_CONTEXT_BUFFER:
- v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER);
- v_context->decode_buffer->context_buffer_address_hi = (addr >> 32);
- v_context->decode_buffer->context_buffer_address_lo = (addr);
- break;
- default:
- igt_info("Not Supported!\n");
- }
-}
-
-static void
-amdgpu_cs_vcn_dec_create(amdgpu_device_handle device_handle, struct mmd_context *context,
- struct vcn_context *v_context)
-{
- struct amdgpu_mmd_bo msg_buf;
- unsigned int ip;
- int len, r;
-
- context->num_resources = 0;
- alloc_resource(device_handle, &msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
- alloc_resource(device_handle, &v_context->session_ctx_buf, 32 * 4096, AMDGPU_GEM_DOMAIN_GTT);
- context->resources[context->num_resources++] = msg_buf.handle;
- context->resources[context->num_resources++] = v_context->session_ctx_buf.handle;
- context->resources[context->num_resources++] = context->ib_handle;
- r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
- igt_assert_eq(r, 0);
-
- memset(msg_buf.ptr, 0, 4096);
- memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
-
- len = 0;
- vcn_dec_cmd(context, v_context, v_context->session_ctx_buf.addr, 5, &len);
- if (context->vcn_dec_sw_ring == true) {
- vcn_dec_cmd(context, v_context, msg_buf.addr, 0, &len);
- } else {
- context->ib_cpu[len++] = reg[context->vcn_reg_index].data0;
- context->ib_cpu[len++] = msg_buf.addr;
- context->ib_cpu[len++] = reg[context->vcn_reg_index].data1;
- context->ib_cpu[len++] = msg_buf.addr >> 32;
- context->ib_cpu[len++] = reg[context->vcn_reg_index].cmd;
- context->ib_cpu[len++] = 0;
- for (; len % 16; ) {
- context->ib_cpu[len++] = reg[context->vcn_reg_index].nop;
- context->ib_cpu[len++] = 0;
- }
- }
- if (context->vcn_unified_ring) {
- amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
- ip = AMDGPU_HW_IP_VCN_ENC;
- } else
- ip = AMDGPU_HW_IP_VCN_DEC;
-
- r = submit(device_handle, context, len, ip);
-
- igt_assert_eq(r, 0);
-
- free_resource(&msg_buf);
-}
-
-static void
-amdgpu_cs_vcn_dec_decode(amdgpu_device_handle device_handle, struct mmd_context *context,
- struct vcn_context *v_context)
-{
- const unsigned int dpb_size = 15923584, dt_size = 737280;
- uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
- struct amdgpu_mmd_bo dec_buf;
- int size, len, i, r;
- unsigned int ip;
- uint8_t *dec;
-
- size = 4*1024; /* msg */
- size += 4*1024; /* fb */
- size += 4096; /*it_scaling_table*/
- size += ALIGN(sizeof(uvd_bitstream), 4*1024);
- size += ALIGN(dpb_size, 4*1024);
- size += ALIGN(dt_size, 4*1024);
-
-
- context->num_resources = 0;
- alloc_resource(device_handle, &dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
- context->resources[context->num_resources++] = dec_buf.handle;
- context->resources[context->num_resources++] = context->ib_handle;
-
- r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
- dec = dec_buf.ptr;
-
- igt_assert_eq(r, 0);
- memset(dec_buf.ptr, 0, size);
- memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
- memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
- avc_decode_msg, sizeof(avc_decode_msg));
-
- dec += 4*1024;
- memcpy(dec, feedback_msg, sizeof(feedback_msg));
- dec += 4*1024;
- memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
-
- dec += 4*1024;
- memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
-
- dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
-
- dec += ALIGN(dpb_size, 4*1024);
-
- msg_addr = dec_buf.addr;
- fb_addr = msg_addr + 4*1024;
- it_addr = fb_addr + 4*1024;
- bs_addr = it_addr + 4*1024;
- dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
- ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
- dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
-
-
- len = 0;
- vcn_dec_cmd(context, v_context, v_context->session_ctx_buf.addr, 0x5, &len);
- vcn_dec_cmd(context, v_context, msg_addr, 0x0, &len);
- vcn_dec_cmd(context, v_context, dpb_addr, 0x1, &len);
- vcn_dec_cmd(context, v_context, dt_addr, 0x2, &len);
- vcn_dec_cmd(context, v_context, fb_addr, 0x3, &len);
- vcn_dec_cmd(context, v_context, bs_addr, 0x100, &len);
- vcn_dec_cmd(context, v_context, it_addr, 0x204, &len);
- vcn_dec_cmd(context, v_context, ctx_addr, 0x206, &len);
-
- if (context->vcn_dec_sw_ring == false) {
- context->ib_cpu[len++] = reg[context->vcn_reg_index].cntl;
- context->ib_cpu[len++] = 0x1;
- for (; len % 16; ) {
- context->ib_cpu[len++] = reg[context->vcn_reg_index].nop;
- context->ib_cpu[len++] = 0;
- }
- }
-
- if (context->vcn_unified_ring) {
- amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
- ip = AMDGPU_HW_IP_VCN_ENC;
- } else
- ip = AMDGPU_HW_IP_VCN_DEC;
-
- r = submit(device_handle, context, len, ip);
- igt_assert_eq(r, 0);
-
- for (i = 0, sum = 0; i < dt_size; ++i)
- sum += dec[i];
-
- igt_assert_eq(sum, SUM_DECODE);
-
- free_resource(&dec_buf);
-}
-
-static void
-amdgpu_cs_vcn_dec_destroy(amdgpu_device_handle device_handle,
- struct mmd_context *context, struct vcn_context *v_context)
-{
- struct amdgpu_mmd_bo msg_buf;
- unsigned int ip;
- int len, r;
-
- context->num_resources = 0;
- alloc_resource(device_handle, &msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
- context->resources[context->num_resources++] = msg_buf.handle;
- context->resources[context->num_resources++] = context->ib_handle;
-
- r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
- igt_assert_eq(r, 0);
-
- memset(msg_buf.ptr, 0, 1024);
- memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
-
- len = 0;
- vcn_dec_cmd(context, v_context, v_context->session_ctx_buf.addr, 5, &len);
- if (context->vcn_dec_sw_ring == true) {
- vcn_dec_cmd(context, v_context, msg_buf.addr, 0, &len);
- } else {
- context->ib_cpu[len++] = reg[context->vcn_reg_index].data0;
- context->ib_cpu[len++] = msg_buf.addr;
- context->ib_cpu[len++] = reg[context->vcn_reg_index].data1;
- context->ib_cpu[len++] = msg_buf.addr >> 32;
- context->ib_cpu[len++] = reg[context->vcn_reg_index].cmd;
- context->ib_cpu[len++] = 0;
- for (; len % 16; ) {
- context->ib_cpu[len++] = reg[context->vcn_reg_index].nop;
- context->ib_cpu[len++] = 0;
- }
- }
- if (context->vcn_unified_ring) {
- amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
- ip = AMDGPU_HW_IP_VCN_ENC;
- } else
- ip = AMDGPU_HW_IP_VCN_DEC;
-
- r = submit(device_handle, context, len, ip);
- igt_assert_eq(r, 0);
-
- free_resource(&msg_buf);
- free_resource(&v_context->session_ctx_buf);
-}
-
static void
amdgpu_cs_vcn_enc_create(amdgpu_device_handle device_handle,
struct mmd_context *context, struct vcn_context *v_context)
@@ -717,130 +233,6 @@ amdgpu_cs_vcn_enc_create(amdgpu_device_handle device_handle,
igt_assert_eq(r, 0);
}
-static void
-amdgpu_cs_vcn_ib_zero_count(struct mmd_context *context, int *len, int num)
-{
- int i;
-
- for (i = 0; i < num; i++)
- context->ib_cpu[(*len)++] = 0;
-}
-
-static int32_t
-h264_se(struct buffer_info *buf_info)
-{
- uint32_t ret, temp;
-
- ret = bs_read_ue(buf_info);
- if ((ret & 0x1) == 0) {
- ret >>= 1;
- temp = 0 - ret;
- return temp;
- }
-
- return (ret + 1) >> 1;
-}
-
-static void
-h264_check_0s(struct buffer_info *buf_info, int count)
-{
- uint32_t val;
-
- val = bs_read_u(buf_info, count);
- if (val != 0)
- igt_info("field error - %d bits should be 0 is %x\n", count, val);
-}
-
-static int
-bs_eof(struct buffer_info *buf_info)
-{
- if (buf_info->dec_buffer >= buf_info->end)
- return 1;
- else
- return 0;
-}
-
-static uint32_t
-bs_read_u1(struct buffer_info *buf_info)
-{
- uint32_t r = 0;
- uint32_t temp = 0;
-
- buf_info->num_bits_in_buffer--;
- if (!bs_eof(buf_info)) {
- temp = (((buf_info->dec_data)) >> buf_info->num_bits_in_buffer);
- r = temp & 0x01;
- }
-
- if (buf_info->num_bits_in_buffer == 0) {
- buf_info->dec_buffer++;
- buf_info->dec_data = *buf_info->dec_buffer;
- buf_info->num_bits_in_buffer = 8;
- }
-
- return r;
-}
-
-static uint32_t
-bs_read_u(struct buffer_info *buf_info, int n)
-{
- uint32_t r = 0;
- int i;
-
- for (i = 0; i < n; i++)
- r |= (bs_read_u1(buf_info) << (n - i - 1));
-
- return r;
-}
-
-static uint32_t
-bs_read_ue(struct buffer_info *buf_info)
-{
- int32_t r = 0;
- int i = 0;
-
- while ((bs_read_u1(buf_info) == 0) && (i < 32) && (!bs_eof(buf_info)))
- i++;
- r = bs_read_u(buf_info, i);
- r += (1 << i) - 1;
- return r;
-}
-
-static uint32_t
-remove_03(uint8_t *bptr, uint32_t len)
-{
- uint32_t nal_len = 0;
-
- while (nal_len + 2 < len) {
- if (bptr[0] == 0 && bptr[1] == 0 && bptr[2] == 3) {
- bptr += 2;
- nal_len += 2;
- len--;
- memmove(bptr, bptr + 1, len - nal_len);
- } else {
- bptr++;
- nal_len++;
- }
- }
- return len;
-}
-
-static void
-scaling_list(uint32_t ix, uint32_t size_scaling_list, struct buffer_info *buf_info)
-{
- uint32_t last_scale = 8, next_scale = 8;
- uint32_t jx;
- int delta_scale;
-
- for (jx = 0; jx < size_scaling_list; jx++) {
- if (next_scale != 0) {
- delta_scale = h264_se(buf_info);
- next_scale = (last_scale + delta_scale + 256) % 256;
- }
- if (next_scale != 0)
- last_scale = next_scale;
- }
-}
static void
h264_parse_sequence_parameter_set(struct h264_decode *dec, struct buffer_info *buf_info)
@@ -857,7 +249,7 @@ h264_parse_sequence_parameter_set(struct h264_decode *dec, struct buffer_info *b
bs_read_u(buf_info, 1); /* constaint_set5_flag */
- h264_check_0s(buf_info, 2);
+ check_0s(buf_info, 2);
dec->level_idc = bs_read_u(buf_info, 8);
bs_read_ue(buf_info); /* SPS id*/
if (dec->profile == 100 || dec->profile == 110 ||
@@ -926,12 +318,12 @@ h264_slice_header(struct h264_decode *dec, struct buffer_info *buf_info)
dec->slice_type = ((temp > 5) ? (temp - 5) : temp);
}
-static uint8_t
+uint8_t
h264_parse_nal(struct h264_decode *dec, struct buffer_info *buf_info)
{
uint8_t type = 0;
- h264_check_0s(buf_info, 1);
+ check_0s(buf_info, 1);
dec->nal_ref_idc = bs_read_u(buf_info, 2);
dec->nal_unit_type = type = bs_read_u(buf_info, 5);
switch (type) {
@@ -955,111 +347,6 @@ h264_parse_nal(struct h264_decode *dec, struct buffer_info *buf_info)
return type;
}
-static uint32_t
-h264_find_next_start_code(uint8_t *pBuf, uint32_t bufLen)
-{
- uint32_t val;
- uint32_t offset, startBytes;
-
- offset = startBytes = 0;
- if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 0 && pBuf[3] == 1) {
- pBuf += 4;
- offset = 4;
- startBytes = 1;
- } else if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 1) {
- pBuf += 3;
- offset = 3;
- startBytes = 1;
- }
- val = 0xffffffff;
- while (offset < bufLen - 3) {
- val <<= 8;
- val |= *pBuf++;
- offset++;
- if (val == H264_START_CODE)
- return offset - 4;
-
- if ((val & 0x00ffffff) == H264_START_CODE)
- return offset - 3;
- }
- if (bufLen - offset <= 3 && startBytes == 0) {
- startBytes = 0;
- return 0;
- }
-
- return offset;
-}
-
-static int
-verify_checksum(struct vcn_context *v_context, uint8_t *buffer, uint32_t buffer_size)
-{
- uint32_t buffer_pos = 0;
- struct h264_decode dec;
- int done = 0;
-
- memset(&dec, 0, sizeof(struct h264_decode));
- do {
- uint32_t ret;
-
- ret = h264_find_next_start_code(buffer + buffer_pos,
- buffer_size - buffer_pos);
- if (ret == 0) {
- done = 1;
- if (buffer_pos == 0)
- igt_info("couldn't find start code in buffer from 0\n");
- } else {
- /* have a complete NAL from buffer_pos to end */
- if (ret > 3) {
- uint32_t nal_len;
- struct buffer_info buf_info;
-
- nal_len = remove_03(buffer + buffer_pos, ret);
- buf_info.dec_buffer = buffer + buffer_pos + (buffer[buffer_pos + 2] == 1 ? 3 : 4);
- buf_info.dec_buffer_size = (nal_len - (buffer[buffer_pos + 2] == 1 ? 3 : 4)) * 8;
- buf_info.end = buffer + buffer_pos + nal_len;
- buf_info.num_bits_in_buffer = 8;
- buf_info.dec_data = *buf_info.dec_buffer;
- h264_parse_nal(&dec, &buf_info);
- }
- buffer_pos += ret; /* buffer_pos points to next code */
- }
- } while (done == 0);
-
- if ((dec.pic_width == v_context->gWidth) &&
- (dec.pic_height == v_context->gHeight) &&
- (dec.slice_type == v_context->gSliceType))
- return 0;
- else
- return -1;
-}
-
-static void
-check_result(struct vcn_context *v_context, struct amdgpu_mmd_bo fb_buf,
- struct amdgpu_mmd_bo bs_buf, int frame_type)
-{
- uint32_t *fb_ptr;
- uint8_t *bs_ptr;
- uint32_t size;
- int r;
-/* uint64_t s[3] = {0, 1121279001727, 1059312481445}; */
-
- r = amdgpu_bo_cpu_map(fb_buf.handle, (void **)&fb_buf.ptr);
- igt_assert_eq(r, 0);
- fb_ptr = (uint32_t *)fb_buf.ptr;
- size = fb_ptr[6];
- r = amdgpu_bo_cpu_unmap(fb_buf.handle);
- igt_assert_eq(r, 0);
- r = amdgpu_bo_cpu_map(bs_buf.handle, (void **)&bs_buf.ptr);
- igt_assert_eq(r, 0);
-
- bs_ptr = (uint8_t *)bs_buf.ptr;
- r = verify_checksum(v_context, bs_ptr, size);
- igt_assert_eq(r, 0);
- r = amdgpu_bo_cpu_unmap(bs_buf.handle);
-
- igt_assert_eq(r, 0);
-}
-
static void
amdgpu_cs_vcn_enc_encode_frame(amdgpu_device_handle device_handle,
struct mmd_context *context, struct vcn_context *v_context,
@@ -1358,7 +645,7 @@ amdgpu_cs_vcn_enc_encode_frame(amdgpu_device_handle device_handle,
igt_assert_eq(r, 0);
/* check result */
- check_result(v_context, fb_buf, bs_buf, frame_type);
+ check_result(v_context, fb_buf, bs_buf, frame_type, IGT_CODEC_TYPE_MPEG4_AVC);
free_resource(&fb_buf);
free_resource(&bs_buf);
@@ -1372,70 +659,6 @@ amdgpu_cs_vcn_enc_encode(amdgpu_device_handle device_handle,
amdgpu_cs_vcn_enc_encode_frame(device_handle, context, v_context, 2); /* IDR frame */
}
-static void
-amdgpu_cs_vcn_enc_destroy(amdgpu_device_handle device_handle, struct mmd_context *context,
- struct vcn_context *v_context)
-{
- int len = 0, r;
- uint32_t *p_task_size = NULL;
- uint32_t task_offset = 0, st_offset;
- uint32_t *st_size = NULL;
- uint32_t fw_maj = 1, fw_min = 9;
-
- if (context->vcn_ip_version_major == 2) {
- fw_maj = 1;
- fw_min = 1;
- } else if (context->vcn_ip_version_major == 3) {
- fw_maj = 1;
- fw_min = 0;
- }
-
- context->num_resources = 0;
- //alloc_resource(&v_context->enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT);
- context->resources[context->num_resources++] = v_context->enc_buf.handle;
- context->resources[context->num_resources++] = context->ib_handle;
-
- if (context->vcn_unified_ring)
- amdgpu_cs_sq_head(v_context, context->ib_cpu, &len, true);
-
- /* session info */
- st_offset = len;
- st_size = &context->ib_cpu[len++]; /* size */
- context->ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */
- context->ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
- context->ib_cpu[len++] = v_context->enc_buf.addr >> 32;
- context->ib_cpu[len++] = v_context->enc_buf.addr;
- context->ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE; */
- *st_size = (len - st_offset) * 4;
-
- /* task info */
- task_offset = len;
- st_offset = len;
- st_size = &context->ib_cpu[len++]; /* size */
- context->ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */
- p_task_size = &context->ib_cpu[len++];
- context->ib_cpu[len++] = v_context->enc_task_id++; /* task_id */
- context->ib_cpu[len++] = 0; /* feedback */
- *st_size = (len - st_offset) * 4;
-
- /* op close */
- st_offset = len;
- st_size = &context->ib_cpu[len++];
- context->ib_cpu[len++] = 0x01000002; /* RENCODE_IB_OP_CLOSE_SESSION */
- *st_size = (len - st_offset) * 4;
-
- *p_task_size = (len - task_offset) * 4;
-
- if (context->vcn_unified_ring)
- amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
-
- r = submit(device_handle, context, len, AMDGPU_HW_IP_VCN_ENC);
- igt_assert_eq(r, 0);
-
- free_resource(&v_context->cpb_buf);
- free_resource(&v_context->enc_buf);
-}
-
igt_main
{
amdgpu_device_handle device;
@@ -1462,9 +685,13 @@ igt_main
igt_subtest_with_dynamic("vcn-decoder-create-decode-destroy") {
if (context.dec_ring) {
igt_dynamic_f("vcn-decoder-create")
- amdgpu_cs_vcn_dec_create(device, &context, &v_context);
+ amdgpu_cs_vcn_dec_create(device, &context, &v_context, vcn_dec_create_msg, \
+ sizeof(vcn_dec_create_msg));
igt_dynamic_f("vcn-decoder-decode")
- amdgpu_cs_vcn_dec_decode(device, &context, &v_context);
+ amdgpu_cs_vcn_dec_decode(device, &context, &v_context, vcn_dec_decode_msg, \
+ sizeof(vcn_dec_decode_msg), avc_decode_msg,sizeof(avc_decode_msg), \
+ feedback_msg, sizeof(feedback_msg), uvd_it_scaling_table, \
+ sizeof(uvd_it_scaling_table), uvd_bitstream, sizeof(uvd_bitstream));
igt_dynamic_f("vcn-decoder-destroy")
amdgpu_cs_vcn_dec_destroy(device, &context, &v_context);
}
@@ -1481,11 +708,40 @@ igt_main
amdgpu_cs_vcn_enc_destroy(device, &context, &v_context);
}
}
+#if 0
+ igt_describe("Test whether vcn hevc decoder is created, decodes, destroyed");
+ igt_subtest_with_dynamic("vcn-hevc-decoder-create-decode-destroy") {
+ if (context.dec_ring) {
+ igt_dynamic_f("vcn-hevc-decoder-create")
+ amdgpu_cs_vcn_dec_create(device, &context, &v_context, vcn_hevc_dec_create_msg, \
+ sizeof(vcn_hevc_dec_create_msg));
+ igt_dynamic_f("vcn-hevc-decoder-decode")
+ amdgpu_cs_vcn_dec_decode(device, &context, &v_context, vcn_hevc_dec_decode_msg, \
+ sizeof(vcn_hevc_dec_decode_msg), hevc_decode_msg,sizeof(hevc_decode_msg), \
+ hevc_feedback_msg, sizeof(hevc_feedback_msg), uvd_it_scaling_table, \
+ sizeof(uvd_it_scaling_table), hevc_bitstream, sizeof(hevc_bitstream));
+ igt_dynamic_f("vcn-hevc-decoder-destroy")
+ amdgpu_cs_vcn_dec_destroy(device, &context, &v_context);
+ }
+ }
+#endif
+ igt_describe("Test whether vcn hevc encoder is created, encodes, destroyed");
+ igt_subtest_with_dynamic("vcn-hevc-encoder-create-encode-destroy") {
+ if (context.enc_ring) {
+ igt_dynamic_f("vcn-hevc-encoder-create")
+ amdgpu_cs_vcn_hevc_enc_create(device, &context, &v_context);
+ igt_dynamic_f("vcn-hevc-encoder-encodes")
+ amdgpu_cs_vcn_hevc_enc_encode(device, &context, &v_context);
+ igt_dynamic_f("vcn-hevc-encoder-destroy")
+ amdgpu_cs_vcn_hevc_enc_destroy(device, &context, &v_context);
+ }
+ }
+
igt_fixture {
mmd_context_clean(device, &context);
amdgpu_device_deinitialize(device);
drm_close_driver(fd);
}
-
}
+
diff --git a/tests/amdgpu/amd_vcn_common.c b/tests/amdgpu/amd_vcn_common.c
new file mode 100644
index 000000000..9275df122
--- /dev/null
+++ b/tests/amdgpu/amd_vcn_common.c
@@ -0,0 +1,727 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ */
+
+#include "lib/amdgpu/amd_mmd_shared.h"
+#include "amd_vcn_common.h"
+#include "amd_vcn_hevc.h"
+
+static struct amdgpu_vcn_reg reg[] = {
+ {0x0, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 0x0, 0x0, 0x0, 0x0},
+ {0x0, 0x0, 0x0, 0x0, 0x0},
+};
+
+bool
+is_vcn_tests_enable(amdgpu_device_handle device_handle, struct mmd_context *context)
+{
+ struct drm_amdgpu_info_hw_ip info;
+ int r;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_ENC, 0, &info);
+
+ if (r)
+ return false;
+
+ context->vcn_ip_version_major = info.hw_ip_version_major;
+ context->vcn_ip_version_minor = info.hw_ip_version_minor;
+ context->enc_ring = !!info.available_rings;
+ /* in vcn 4.0 it re-uses encoding queue as unified queue */
+ if (context->vcn_ip_version_major >= 4) {
+ context->vcn_unified_ring = true;
+ context->vcn_dec_sw_ring = true;
+ context->dec_ring = context->enc_ring;
+ } else {
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
+ context->dec_ring = !!info.available_rings;
+ }
+
+ if (!(context->dec_ring || context->enc_ring) ||
+ (context->family_id < AMDGPU_FAMILY_RV &&
+ (context->family_id == AMDGPU_FAMILY_AI &&
+ (context->chip_id - context->chip_rev) < 0x32))) { /* Arcturus */
+ igt_info("The ASIC does NOT support VCN, vcn test is disabled\n");
+ return false;
+ }
+
+ if (context->family_id == AMDGPU_FAMILY_AI)
+ context->enc_ring = false;
+
+ if (!context->dec_ring) {
+ igt_info("VCN Tests DEC create disable");
+ igt_info("VCN Tests DEC decode disable");
+ igt_info("VCN Tests DEC destroy disable");
+ }
+
+ if (!context->enc_ring) {
+ igt_info("VCN Tests ENC create disable");
+ igt_info("VCN Tests ENC encode disable");
+ igt_info("VCN Tests ENC destroy disable");
+ }
+
+ if (context->vcn_ip_version_major == 1) {
+ context->vcn_reg_index = 0;
+ } else if (context->vcn_ip_version_major == 2 && context->vcn_ip_version_minor == 0) {
+ context->vcn_reg_index = 1;
+ } else if ((context->vcn_ip_version_major == 2 && context->vcn_ip_version_minor >= 5) ||
+ context->vcn_ip_version_major == 3) {
+ context->vcn_reg_index = 2;
+ }
+
+ return true;
+}
+
+void
+amdgpu_cs_sq_head(struct vcn_context *v_context, uint32_t *base, int *offset, bool enc)
+{
+ /* signature */
+ *(base + (*offset)++) = 0x00000010;
+ *(base + (*offset)++) = 0x30000002;
+ v_context->ib_checksum = base + (*offset)++;
+ v_context->ib_size_in_dw = base + (*offset)++;
+
+ /* engine info */
+ *(base + (*offset)++) = 0x00000010;
+ *(base + (*offset)++) = 0x30000001;
+ *(base + (*offset)++) = enc ? 2 : 3;
+ *(base + (*offset)++) = 0x00000000;
+}
+
+void
+amdgpu_cs_sq_ib_tail(struct vcn_context *v_context, uint32_t *end)
+{
+ uint32_t size_in_dw;
+ uint32_t checksum = 0;
+
+ /* if the pointers are invalid, no need to process */
+ if (v_context->ib_checksum == NULL || v_context->ib_size_in_dw == NULL)
+ return;
+
+ size_in_dw = end - v_context->ib_size_in_dw - 1;
+ *v_context->ib_size_in_dw = size_in_dw;
+ *(v_context->ib_size_in_dw + 4) = size_in_dw * sizeof(uint32_t);
+
+ for (int i = 0; i < size_in_dw; i++)
+ checksum += *(v_context->ib_checksum + 2 + i);
+
+ *v_context->ib_checksum = checksum;
+
+ v_context->ib_checksum = NULL;
+ v_context->ib_size_in_dw = NULL;
+}
+
+void
+vcn_dec_cmd(struct mmd_context *context, struct vcn_context *v_context,
+ uint64_t addr, unsigned int cmd, int *idx)
+{
+ if (context->vcn_dec_sw_ring == false) {
+ context->ib_cpu[(*idx)++] = reg[context->vcn_reg_index].data0;
+ context->ib_cpu[(*idx)++] = addr;
+ context->ib_cpu[(*idx)++] = reg[context->vcn_reg_index].data1;
+ context->ib_cpu[(*idx)++] = addr >> 32;
+ context->ib_cpu[(*idx)++] = reg[context->vcn_reg_index].cmd;
+ context->ib_cpu[(*idx)++] = cmd << 1;
+ return;
+ }
+
+ /* Support decode software ring message */
+ if (!(*idx)) {
+ struct rvcn_decode_ib_package *ib_header;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_head(v_context, context->ib_cpu, idx, false);
+
+ ib_header = (struct rvcn_decode_ib_package *)&context->ib_cpu[*idx];
+ ib_header->package_size = sizeof(struct rvcn_decode_buffer) +
+ sizeof(struct rvcn_decode_ib_package);
+
+ (*idx)++;
+ ib_header->package_type = (DECODE_IB_PARAM_DECODE_BUFFER);
+ (*idx)++;
+
+ v_context->decode_buffer = (struct rvcn_decode_buffer *)&(context->ib_cpu[*idx]);
+ *idx += sizeof(struct rvcn_decode_buffer) / 4;
+ memset(v_context->decode_buffer, 0, sizeof(struct rvcn_decode_buffer));
+ }
+
+ switch (cmd) {
+ case DECODE_CMD_MSG_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= DECODE_CMDBUF_FLAGS_MSG_BUFFER;
+ v_context->decode_buffer->msg_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->msg_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_DPB_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DPB_BUFFER);
+ v_context->decode_buffer->dpb_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->dpb_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_DECODING_TARGET_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER);
+ v_context->decode_buffer->target_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->target_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_FEEDBACK_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER);
+ v_context->decode_buffer->feedback_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->feedback_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_PROB_TBL_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER);
+ v_context->decode_buffer->prob_tbl_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->prob_tbl_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_SESSION_CONTEXT_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER);
+ v_context->decode_buffer->session_contex_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->session_contex_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_BITSTREAM_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER);
+ v_context->decode_buffer->bitstream_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->bitstream_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_IT_SCALING_TABLE_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER);
+ v_context->decode_buffer->it_sclr_table_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->it_sclr_table_buffer_address_lo = (addr);
+ break;
+ case DECODE_CMD_CONTEXT_BUFFER:
+ v_context->decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER);
+ v_context->decode_buffer->context_buffer_address_hi = (addr >> 32);
+ v_context->decode_buffer->context_buffer_address_lo = (addr);
+ break;
+ default:
+ igt_info("Not Supported!\n");
+ }
+}
+
+void
+amdgpu_cs_vcn_dec_create(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context, const uint8_t *dec_create_msg, int size)
+{
+ struct amdgpu_mmd_bo msg_buf;
+ unsigned int ip;
+ int len, r;
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &v_context->session_ctx_buf, 32 * 4096, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = msg_buf.handle;
+ context->resources[context->num_resources++] = v_context->session_ctx_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+ r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
+ igt_assert_eq(r, 0);
+
+ memset(msg_buf.ptr, 0, 4096);
+ memcpy(msg_buf.ptr, dec_create_msg, size);
+
+ len = 0;
+ vcn_dec_cmd(context, v_context, v_context->session_ctx_buf.addr, 5, &len);
+ if (context->vcn_dec_sw_ring == true) {
+ vcn_dec_cmd(context, v_context, msg_buf.addr, 0, &len);
+ } else {
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].data0;
+ context->ib_cpu[len++] = msg_buf.addr;
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].data1;
+ context->ib_cpu[len++] = msg_buf.addr >> 32;
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].cmd;
+ context->ib_cpu[len++] = 0;
+ for (; len % 16; ) {
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].nop;
+ context->ib_cpu[len++] = 0;
+ }
+ }
+ if (context->vcn_unified_ring) {
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+ ip = AMDGPU_HW_IP_VCN_ENC;
+ } else{
+ ip = AMDGPU_HW_IP_VCN_DEC;}
+
+ r = submit(device_handle, context, len, ip);
+
+ igt_assert_eq(r, 0);
+
+ free_resource(&msg_buf);
+}
+
+void
+amdgpu_cs_vcn_dec_decode(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context, const uint8_t *p_vcn_dec_decode_msg,
+ int vcn_dec_decode_msg_size, const uint8_t *p_avc_decode_msg,
+ int avc_decode_msg_size, const uint8_t *p_feedback_msg,
+ int feedback_msg_size, const uint8_t *p_uvd_it_scaling_table,
+ int uvd_it_scaling_table_size, const uint8_t *p_uvd_bitstream,
+ int uvd_bitstream_size)
+{
+ const unsigned int dpb_size = 15923584, dt_size = 737280;
+ uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
+ struct amdgpu_mmd_bo dec_buf;
+ int size, len, i, r;
+ unsigned int ip;
+ uint8_t *dec;
+
+ size = 4*1024; /* msg */
+ size += 4*1024; /* fb */
+ size += 4096; /*it_scaling_table*/
+ size += ALIGN(uvd_bitstream_size, 4*1024);
+ size += ALIGN(dpb_size, 4*1024);
+ size += ALIGN(dt_size, 4*1024);
+
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = dec_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
+ dec = dec_buf.ptr;
+
+ igt_assert_eq(r, 0);
+ memset(dec_buf.ptr, 0, size);
+ memcpy(dec_buf.ptr, p_vcn_dec_decode_msg, vcn_dec_decode_msg_size);
+ memcpy(dec_buf.ptr + vcn_dec_decode_msg_size,
+ p_avc_decode_msg, avc_decode_msg_size);
+
+ dec += 4*1024;
+ memcpy(dec, p_feedback_msg, feedback_msg_size);
+ dec += 4*1024;
+ memcpy(dec, p_uvd_it_scaling_table, uvd_it_scaling_table_size);
+
+ dec += 4*1024;
+ memcpy(dec, p_uvd_bitstream, uvd_bitstream_size);
+
+ dec += ALIGN(uvd_bitstream_size, 4*1024);
+
+ dec += ALIGN(dpb_size, 4*1024);
+
+ msg_addr = dec_buf.addr;
+ fb_addr = msg_addr + 4*1024;
+ it_addr = fb_addr + 4*1024;
+ bs_addr = it_addr + 4*1024;
+ dpb_addr = ALIGN(bs_addr + uvd_bitstream_size, 4*1024);
+ ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
+ dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
+
+
+ len = 0;
+ vcn_dec_cmd(context, v_context, v_context->session_ctx_buf.addr, 0x5, &len);
+ vcn_dec_cmd(context, v_context, msg_addr, 0x0, &len);
+ vcn_dec_cmd(context, v_context, dpb_addr, 0x1, &len);
+ vcn_dec_cmd(context, v_context, dt_addr, 0x2, &len);
+ vcn_dec_cmd(context, v_context, fb_addr, 0x3, &len);
+ vcn_dec_cmd(context, v_context, bs_addr, 0x100, &len);
+ vcn_dec_cmd(context, v_context, it_addr, 0x204, &len);
+ vcn_dec_cmd(context, v_context, ctx_addr, 0x206, &len);
+
+ if (context->vcn_dec_sw_ring == false) {
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].cntl;
+ context->ib_cpu[len++] = 0x1;
+ for (; len % 16; ) {
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].nop;
+ context->ib_cpu[len++] = 0;
+ }
+ }
+
+ if (context->vcn_unified_ring) {
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+ ip = AMDGPU_HW_IP_VCN_ENC;
+ } else
+ ip = AMDGPU_HW_IP_VCN_DEC;
+
+ r = submit(device_handle, context, len, ip);
+ igt_assert_eq(r, 0);
+
+ for (i = 0, sum = 0; i < dt_size; ++i)
+ sum += dec[i];
+
+ igt_assert_eq(sum, SUM_DECODE);
+
+ free_resource(&dec_buf);
+}
+
+void
+amdgpu_cs_vcn_dec_destroy(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context)
+{
+ struct amdgpu_mmd_bo msg_buf;
+ unsigned int ip;
+ int len, r;
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = msg_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
+ igt_assert_eq(r, 0);
+
+ memset(msg_buf.ptr, 0, 1024);
+ memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
+
+ len = 0;
+ vcn_dec_cmd(context, v_context, v_context->session_ctx_buf.addr, 5, &len);
+ if (context->vcn_dec_sw_ring == true) {
+ vcn_dec_cmd(context, v_context, msg_buf.addr, 0, &len);
+ } else {
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].data0;
+ context->ib_cpu[len++] = msg_buf.addr;
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].data1;
+ context->ib_cpu[len++] = msg_buf.addr >> 32;
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].cmd;
+ context->ib_cpu[len++] = 0;
+ for (; len % 16; ) {
+ context->ib_cpu[len++] = reg[context->vcn_reg_index].nop;
+ context->ib_cpu[len++] = 0;
+ }
+ }
+ if (context->vcn_unified_ring) {
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+ ip = AMDGPU_HW_IP_VCN_ENC;
+ } else
+ ip = AMDGPU_HW_IP_VCN_DEC;
+
+ r = submit(device_handle, context, len, ip);
+ igt_assert_eq(r, 0);
+
+ free_resource(&msg_buf);
+ free_resource(&v_context->session_ctx_buf);
+}
+
+void
+amdgpu_cs_vcn_ib_zero_count(struct mmd_context *context, int *len, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ context->ib_cpu[(*len)++] = 0;
+}
+
+int32_t
+h264_se(struct buffer_info *buf_info)
+{
+ uint32_t ret, temp;
+
+ ret = bs_read_ue(buf_info);
+ if ((ret & 0x1) == 0) {
+ ret >>= 1;
+ temp = 0 - ret;
+ return temp;
+ }
+
+ return (ret + 1) >> 1;
+}
+
+void
+check_0s(struct buffer_info *buf_info, int count)
+{
+ uint32_t val;
+
+ val = bs_read_u(buf_info, count);
+ if (val != 0)
+ igt_info("field error - %d bits should be 0 is %x\n", count, val);
+}
+
+int
+bs_eof(struct buffer_info *buf_info)
+{
+ if (buf_info->dec_buffer >= buf_info->end)
+ return 1;
+ else
+ return 0;
+}
+
+uint32_t
+bs_read_u1(struct buffer_info *buf_info)
+{
+ uint32_t r = 0;
+ uint32_t temp = 0;
+
+ buf_info->num_bits_in_buffer--;
+ if (!bs_eof(buf_info)) {
+ temp = (((buf_info->dec_data)) >> buf_info->num_bits_in_buffer);
+ r = temp & 0x01;
+ }
+
+ if (buf_info->num_bits_in_buffer == 0) {
+ buf_info->dec_buffer++;
+ buf_info->dec_data = *buf_info->dec_buffer;
+ buf_info->num_bits_in_buffer = 8;
+ }
+
+ return r;
+}
+
+uint32_t
+bs_read_u(struct buffer_info *buf_info, int n)
+{
+ uint32_t r = 0;
+ int i;
+
+ for (i = 0; i < n; i++)
+ r |= (bs_read_u1(buf_info) << (n - i - 1));
+
+ return r;
+}
+
+uint32_t
+bs_read_ue(struct buffer_info *buf_info)
+{
+ int32_t r = 0;
+ int i = 0;
+
+ while ((bs_read_u1(buf_info) == 0) && (i < 32) && (!bs_eof(buf_info)))
+ i++;
+ r = bs_read_u(buf_info, i);
+ r += (1 << i) - 1;
+ return r;
+}
+
+uint32_t
+remove_03(uint8_t *bptr, uint32_t len)
+{
+ uint32_t nal_len = 0;
+
+ while (nal_len + 2 < len) {
+ if (bptr[0] == 0 && bptr[1] == 0 && bptr[2] == 3) {
+ bptr += 2;
+ nal_len += 2;
+ len--;
+ memmove(bptr, bptr + 1, len - nal_len);
+ } else {
+ bptr++;
+ nal_len++;
+ }
+ }
+ return len;
+}
+
+void
+scaling_list(uint32_t ix, uint32_t size_scaling_list, struct buffer_info *buf_info)
+{
+ uint32_t last_scale = 8, next_scale = 8;
+ uint32_t jx;
+ int delta_scale;
+
+ for (jx = 0; jx < size_scaling_list; jx++) {
+ if (next_scale != 0) {
+ delta_scale = h264_se(buf_info);
+ next_scale = (last_scale + delta_scale + 256) % 256;
+ }
+ if (next_scale != 0)
+ last_scale = next_scale;
+ }
+}
+
+
+static uint32_t
+h264_find_next_start_code(uint8_t *pBuf, uint32_t bufLen)
+{
+ uint32_t val;
+ uint32_t offset, startBytes;
+
+ offset = startBytes = 0;
+ if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 0 && pBuf[3] == 1) {
+ pBuf += 4;
+ offset = 4;
+ startBytes = 1;
+ } else if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 1) {
+ pBuf += 3;
+ offset = 3;
+ startBytes = 1;
+ }
+ val = 0xffffffff;
+ while (offset < bufLen - 3) {
+ val <<= 8;
+ val |= *pBuf++;
+ offset++;
+ if (val == H264_START_CODE)
+ return offset - 4;
+ if ((val & 0x00ffffff) == H264_START_CODE)
+ return offset - 3;
+ }
+ if (bufLen - offset <= 3 && startBytes == 0) {
+ startBytes = 0;
+ return 0;
+ }
+
+ return offset;
+}
+
+static int
+verify_checksum(struct vcn_context *v_context, uint8_t *buffer, uint32_t buffer_size, igt_codec_type_e codec_type)
+{
+ uint32_t buffer_pos = 0;
+ struct h264_decode dec;
+ struct hevc_decode hevc_dec;
+ int done = 0;
+ int ret_val = -1;
+
+ memset(&dec, 0, sizeof(struct h264_decode));
+ memset(&hevc_dec, 0, sizeof(struct hevc_decode));
+ do {
+ uint32_t ret;
+
+ ret = h264_find_next_start_code(buffer + buffer_pos,
+ buffer_size - buffer_pos);
+ if (ret == 0) {
+ done = 1;
+ if (buffer_pos == 0)
+ igt_info("couldn't find start code in buffer from 0\n");
+ } else {
+ /* have a complete NAL from buffer_pos to end */
+ if (ret > 3) {
+ uint32_t nal_len;
+ struct buffer_info buf_info;
+
+ nal_len = remove_03(buffer + buffer_pos, ret);
+ buf_info.dec_buffer = buffer + buffer_pos + (buffer[buffer_pos + 2] == 1 ? 3 : 4);
+ buf_info.dec_buffer_size = (nal_len - (buffer[buffer_pos + 2] == 1 ? 3 : 4)) * 8;
+ buf_info.end = buffer + buffer_pos + nal_len;
+ buf_info.num_bits_in_buffer = 8;
+ buf_info.dec_data = *buf_info.dec_buffer;
+ switch(codec_type) {
+ case IGT_CODEC_TYPE_MPEG4_AVC:
+ h264_parse_nal(&dec, &buf_info);
+ break;
+ case IGT_CODEC_TYPE_HEVC:
+ hevc_parse_nal(&hevc_dec, &buf_info);
+ break;
+ default:
+ /*NOP*/
+ break;
+ }
+
+ }
+ buffer_pos += ret; /* buffer_pos points to next code */
+ }
+ } while (done == 0);
+
+ switch(codec_type) {
+ case IGT_CODEC_TYPE_MPEG4_AVC:
+
+ if ((dec.pic_width == v_context->gWidth) &&
+ (dec.pic_height == v_context->gHeight) &&
+ (dec.slice_type == v_context->gSliceType))
+ ret_val = 0;
+ else
+ ret_val = -1;
+
+ break;
+ case IGT_CODEC_TYPE_HEVC:
+ if ((hevc_dec.pic_width == v_context->gWidth) &&
+ (hevc_dec.pic_height == v_context->gHeight) &&
+ (hevc_dec.slice_type == v_context->gSliceType))
+ ret_val = 0;
+ else
+ ret_val = -1;
+ break;
+ default:
+ /* NOP */
+ break;
+ }
+ return ret_val;
+}
+
+void
+check_result(struct vcn_context *v_context, struct amdgpu_mmd_bo fb_buf,
+ struct amdgpu_mmd_bo bs_buf, int frame_type, igt_codec_type_e codec_type)
+{
+ uint32_t *fb_ptr;
+ uint8_t *bs_ptr;
+ uint32_t size;
+ int r;
+/* uint64_t s[3] = {0, 1121279001727, 1059312481445}; */
+
+ r = amdgpu_bo_cpu_map(fb_buf.handle, (void **)&fb_buf.ptr);
+ igt_assert_eq(r, 0);
+ fb_ptr = (uint32_t *)fb_buf.ptr;
+ size = fb_ptr[6];
+ r = amdgpu_bo_cpu_unmap(fb_buf.handle);
+ igt_assert_eq(r, 0);
+ r = amdgpu_bo_cpu_map(bs_buf.handle, (void **)&bs_buf.ptr);
+ igt_assert_eq(r, 0);
+
+ bs_ptr = (uint8_t *)bs_buf.ptr;
+
+ switch(codec_type) {
+ case IGT_CODEC_TYPE_MPEG4_AVC:
+ r = verify_checksum(v_context, bs_ptr, size, IGT_CODEC_TYPE_MPEG4_AVC);
+ break;
+ case IGT_CODEC_TYPE_HEVC:
+ r = verify_checksum(v_context, bs_ptr, size, IGT_CODEC_TYPE_HEVC);
+ break;
+ default:
+ /*NOP*/
+ break;
+ }
+ igt_assert_eq(r, 0);
+ r = amdgpu_bo_cpu_unmap(bs_buf.handle);
+
+ igt_assert_eq(r, 0);
+}
+
+
+void
+amdgpu_cs_vcn_enc_destroy(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context)
+{
+ int len = 0, r;
+ uint32_t *p_task_size = NULL;
+ uint32_t task_offset = 0, st_offset;
+ uint32_t *st_size = NULL;
+ uint32_t fw_maj = 1, fw_min = 9;
+
+ if (context->vcn_ip_version_major == 2) {
+ fw_maj = 1;
+ fw_min = 1;
+ } else if (context->vcn_ip_version_major == 3) {
+ fw_maj = 1;
+ fw_min = 0;
+ }
+
+ context->num_resources = 0;
+ //alloc_resource(&v_context->enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = v_context->enc_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_head(v_context, context->ib_cpu, &len, true);
+
+ /* session info */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */
+ context->ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
+ context->ib_cpu[len++] = v_context->enc_buf.addr >> 32;
+ context->ib_cpu[len++] = v_context->enc_buf.addr;
+ context->ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE; */
+ *st_size = (len - st_offset) * 4;
+
+ /* task info */
+ task_offset = len;
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */
+ p_task_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = v_context->enc_task_id++; /* task_id */
+ context->ib_cpu[len++] = 0; /* feedback */
+ *st_size = (len - st_offset) * 4;
+
+ /* op close */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = 0x01000002; /* RENCODE_IB_OP_CLOSE_SESSION */
+ *st_size = (len - st_offset) * 4;
+
+ *p_task_size = (len - task_offset) * 4;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+
+ r = submit(device_handle, context, len, AMDGPU_HW_IP_VCN_ENC);
+ igt_assert_eq(r, 0);
+
+ free_resource(&v_context->cpb_buf);
+ free_resource(&v_context->enc_buf);
+}
diff --git a/tests/amdgpu/amd_vcn_common.h b/tests/amdgpu/amd_vcn_common.h
new file mode 100644
index 000000000..bb2ca8825
--- /dev/null
+++ b/tests/amdgpu/amd_vcn_common.h
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ */
+
+
+#define DECODE_CMD_MSG_BUFFER 0x00000000
+#define DECODE_CMD_DPB_BUFFER 0x00000001
+#define DECODE_CMD_DECODING_TARGET_BUFFER 0x00000002
+#define DECODE_CMD_FEEDBACK_BUFFER 0x00000003
+#define DECODE_CMD_PROB_TBL_BUFFER 0x00000004
+#define DECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005
+#define DECODE_CMD_BITSTREAM_BUFFER 0x00000100
+#define DECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204
+#define DECODE_CMD_CONTEXT_BUFFER 0x00000206
+
+#define DECODE_IB_PARAM_DECODE_BUFFER (0x00000001)
+
+#define DECODE_CMDBUF_FLAGS_MSG_BUFFER (0x00000001)
+#define DECODE_CMDBUF_FLAGS_DPB_BUFFER (0x00000002)
+#define DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER (0x00000004)
+#define DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER (0x00000008)
+#define DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER (0x00000010)
+#define DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER (0x00000200)
+#define DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER (0x00000800)
+#define DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER (0x00001000)
+#define DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER (0x00100000)
+
+#define H264_START_CODE 0x000001
+
+typedef enum {
+ IGT_CODEC_TYPE_MPEG4_AVC = 0,
+ IGT_CODEC_TYPE_HEVC = 1,
+} igt_codec_type_e;
+
+struct rvcn_decode_buffer {
+ unsigned int valid_buf_flag;
+ unsigned int msg_buffer_address_hi;
+ unsigned int msg_buffer_address_lo;
+ unsigned int dpb_buffer_address_hi;
+ unsigned int dpb_buffer_address_lo;
+ unsigned int target_buffer_address_hi;
+ unsigned int target_buffer_address_lo;
+ unsigned int session_contex_buffer_address_hi;
+ unsigned int session_contex_buffer_address_lo;
+ unsigned int bitstream_buffer_address_hi;
+ unsigned int bitstream_buffer_address_lo;
+ unsigned int context_buffer_address_hi;
+ unsigned int context_buffer_address_lo;
+ unsigned int feedback_buffer_address_hi;
+ unsigned int feedback_buffer_address_lo;
+ unsigned int luma_hist_buffer_address_hi;
+ unsigned int luma_hist_buffer_address_lo;
+ unsigned int prob_tbl_buffer_address_hi;
+ unsigned int prob_tbl_buffer_address_lo;
+ unsigned int sclr_coeff_buffer_address_hi;
+ unsigned int sclr_coeff_buffer_address_lo;
+ unsigned int it_sclr_table_buffer_address_hi;
+ unsigned int it_sclr_table_buffer_address_lo;
+ unsigned int sclr_target_buffer_address_hi;
+ unsigned int sclr_target_buffer_address_lo;
+ unsigned int cenc_size_info_buffer_address_hi;
+ unsigned int cenc_size_info_buffer_address_lo;
+ unsigned int mpeg2_pic_param_buffer_address_hi;
+ unsigned int mpeg2_pic_param_buffer_address_lo;
+ unsigned int mpeg2_mb_control_buffer_address_hi;
+ unsigned int mpeg2_mb_control_buffer_address_lo;
+ unsigned int mpeg2_idct_coeff_buffer_address_hi;
+ unsigned int mpeg2_idct_coeff_buffer_address_lo;
+};
+
+struct rvcn_decode_ib_package {
+ unsigned int package_size;
+ unsigned int package_type;
+};
+
+
+struct amdgpu_vcn_reg {
+ uint32_t data0;
+ uint32_t data1;
+ uint32_t cmd;
+ uint32_t nop;
+ uint32_t cntl;
+};
+
+struct buffer_info {
+ uint32_t num_bits_in_buffer;
+ const uint8_t *dec_buffer;
+ uint8_t dec_data;
+ uint32_t dec_buffer_size;
+ const uint8_t *end;
+};
+
+
+struct vcn_context {
+ struct amdgpu_mmd_bo enc_buf;
+ struct amdgpu_mmd_bo cpb_buf;
+ struct amdgpu_mmd_bo session_ctx_buf;
+ uint32_t enc_task_id;
+ uint32_t *ib_checksum;
+ uint32_t *ib_size_in_dw;
+ uint32_t gWidth, gHeight, gSliceType;
+ struct rvcn_decode_buffer *decode_buffer;
+};
+
+struct h264_decode {
+ uint8_t profile;
+ uint8_t level_idc;
+ uint8_t nal_ref_idc;
+ uint8_t nal_unit_type;
+ uint32_t pic_width, pic_height;
+ uint32_t slice_type;
+};
+
+struct hevc_decode {
+ uint8_t profile;
+ uint8_t level_idc;
+ uint8_t nal_unit_type;
+ uint32_t pic_width, pic_height;
+ uint32_t slice_type;
+ uint32_t dependent_slice_segments_enabled_flag;
+ uint32_t num_extra_slice_header_bits;
+};
+
+void
+amdgpu_cs_sq_head(struct vcn_context *v_context, uint32_t *base, int *offset, bool enc);
+
+void
+vcn_dec_cmd(struct mmd_context *context, struct vcn_context *v_context,
+ uint64_t addr, unsigned int cmd, int *idx);
+void
+amdgpu_cs_sq_ib_tail(struct vcn_context *v_context, uint32_t *end);
+
+uint32_t
+bs_read_ue(struct buffer_info *buf_info);
+
+int
+bs_eof(struct buffer_info *buf_info);
+
+uint32_t
+bs_read_u1(struct buffer_info *buf_info);
+
+uint32_t
+bs_read_u(struct buffer_info *buf_info, int n);
+
+uint32_t
+remove_03(uint8_t *bptr, uint32_t len);
+
+void
+amdgpu_cs_vcn_ib_zero_count(struct mmd_context *context, int *len, int num);
+
+void
+check_0s(struct buffer_info *buf_info, int count);
+
+int32_t
+h264_se(struct buffer_info *buf_info);
+
+void
+check_result(struct vcn_context *v_context, struct amdgpu_mmd_bo fb_buf,
+ struct amdgpu_mmd_bo bs_buf, int frame_type, igt_codec_type_e codec_type);
+void
+scaling_list(uint32_t ix, uint32_t size_scaling_list, struct buffer_info *buf_info);
+
+bool
+is_vcn_tests_enable(amdgpu_device_handle device_handle, struct mmd_context *context);
+
+void
+amdgpu_cs_vcn_dec_create(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context, const uint8_t *dec_create_msg, int size);
+void
+amdgpu_cs_vcn_dec_decode(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context, const uint8_t *p_vcn_dec_decode_msg,
+ int vcn_dec_decode_msg_size, const uint8_t *p_avc_decode_msg,
+ int avc_decode_msg_size, const uint8_t *p_feedback_msg,
+ int feedback_msg_size, const uint8_t *p_uvd_it_scaling_table,
+ int uvd_it_scaling_table_size, const uint8_t *p_uvd_bitstream,
+ int uvd_bitstream_size);
+void
+amdgpu_cs_vcn_dec_destroy(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context);
+void
+amdgpu_cs_vcn_enc_destroy(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context);
+
+uint8_t
+h264_parse_nal(struct h264_decode *dec, struct buffer_info *buf_info);
diff --git a/tests/amdgpu/amd_vcn_hevc.c b/tests/amdgpu/amd_vcn_hevc.c
new file mode 100644
index 000000000..23ed61d1e
--- /dev/null
+++ b/tests/amdgpu/amd_vcn_hevc.c
@@ -0,0 +1,887 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ */
+
+#include "lib/amdgpu/amd_mmd_shared.h"
+#include "amd_vcn_common.h"
+#include "amd_vcn_hevc.h"
+
+static void profile_tier_level(uint32_t profilePresentFlag, uint32_t maxNumSubLayersMinus1, struct buffer_info *buf_info)
+{
+ uint32_t sub_layer_profile_idc[maxNumSubLayersMinus1];
+ uint32_t sub_layer_profile_present_flag[maxNumSubLayersMinus1];
+ uint32_t sub_layer_level_present_flag[maxNumSubLayersMinus1];
+ uint32_t sub_layer_profile_compatibility_flag[maxNumSubLayersMinus1][32];
+ uint32_t general_profile_compatibility_flag[ 32 ];
+ uint32_t general_profile_idc = 0;
+ int i = 0;
+ int j = 0;
+ if( profilePresentFlag ) {
+ bs_read_u(buf_info, 2); /* general_profile_space */
+ bs_read_u(buf_info, 1); /* general_tier_flag */
+ general_profile_idc = bs_read_u(buf_info, 5); /* general_profile_idc */
+ for(j=0;j<32;j++)
+ general_profile_compatibility_flag[j] = bs_read_u(buf_info,1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ if( general_profile_idc == 4 || general_profile_compatibility_flag[4] ||
+ general_profile_idc == 5 || general_profile_compatibility_flag[5] ||
+ general_profile_idc == 6 || general_profile_compatibility_flag[6] ||
+ general_profile_idc == 7 || general_profile_compatibility_flag[7] ||
+ general_profile_idc == 8 || general_profile_compatibility_flag[8] ||
+ general_profile_idc == 9 || general_profile_compatibility_flag[9] ||
+ general_profile_idc == 10 || general_profile_compatibility_flag[10] ||
+ general_profile_idc == 11 || general_profile_compatibility_flag[11]){
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ if(general_profile_idc == 5 || general_profile_compatibility_flag[5] ||
+ general_profile_idc == 9 || general_profile_compatibility_flag[9] ||
+ general_profile_idc == 10 || general_profile_compatibility_flag[10] ||
+ general_profile_idc == 11 || general_profile_compatibility_flag[11])
+ {
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 33);
+ }
+ else
+ bs_read_u(buf_info, 34);
+ } else if(general_profile_idc == 2 || general_profile_compatibility_flag[2]) {
+ bs_read_u(buf_info, 7);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 35);
+ }
+ else
+ bs_read_u(buf_info, 43);
+
+ if( general_profile_idc == 1 || general_profile_compatibility_flag[1] ||
+ general_profile_idc == 2 || general_profile_compatibility_flag[2] ||
+ general_profile_idc == 3 || general_profile_compatibility_flag[3] ||
+ general_profile_idc == 4 || general_profile_compatibility_flag[4] ||
+ general_profile_idc == 5 || general_profile_compatibility_flag[5] ||
+ general_profile_idc == 9 || general_profile_compatibility_flag[9] ||
+ general_profile_idc == 11|| general_profile_compatibility_flag[11])
+ bs_read_u(buf_info, 1);
+ else
+ bs_read_u(buf_info, 1);
+ }
+ bs_read_u(buf_info, 8); /* general_level_idc */
+ for( i = 0; i < maxNumSubLayersMinus1; i++ ) {
+ sub_layer_profile_present_flag[i] = bs_read_u(buf_info, 1); /* sub_layer_profile_present_flag[ i ] */
+ sub_layer_level_present_flag[i] = bs_read_u(buf_info, 1); /* sub_layer_level_present_flag[ i ] */
+ }
+ if(maxNumSubLayersMinus1 > 0)
+ for(i = maxNumSubLayersMinus1; i < 8; i++)
+ bs_read_u(buf_info, 2);
+ for( i = 0; i < maxNumSubLayersMinus1; i++ ) {
+ if( sub_layer_profile_present_flag[i] ) {
+ bs_read_u(buf_info, 2);
+ bs_read_u(buf_info, 1);
+ sub_layer_profile_idc[i] = bs_read_u(buf_info, 5);
+ for( j = 0; j < 32; j++ )
+ sub_layer_profile_compatibility_flag[i][j] = bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ if( sub_layer_profile_idc[i] == 4 || sub_layer_profile_compatibility_flag[i][4] ||
+ sub_layer_profile_idc[i] == 5 || sub_layer_profile_compatibility_flag[i][5] ||
+ sub_layer_profile_idc[i] == 6 || sub_layer_profile_compatibility_flag[i][6] ||
+ sub_layer_profile_idc[i] == 7 || sub_layer_profile_compatibility_flag[i][7] ||
+ sub_layer_profile_idc[i] == 8 || sub_layer_profile_compatibility_flag[i][8] ||
+ sub_layer_profile_idc[i] == 9 || sub_layer_profile_compatibility_flag[i][9] ||
+ sub_layer_profile_idc[i] == 10|| sub_layer_profile_compatibility_flag[i][10] ||
+ sub_layer_profile_idc[i] == 11|| sub_layer_profile_compatibility_flag[i][11])
+ {
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 1);
+ if( sub_layer_profile_idc[i] == 5 || sub_layer_profile_compatibility_flag[ i ][ 5 ] ||
+ sub_layer_profile_idc[i] == 9 || sub_layer_profile_compatibility_flag[i][9] ||
+ sub_layer_profile_idc[i] == 10 || sub_layer_profile_compatibility_flag[i][10] ||
+ sub_layer_profile_idc[i] == 11 || sub_layer_profile_compatibility_flag[i][11] )
+ {
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 33);
+ }
+ else
+ bs_read_u(buf_info, 34);
+ }
+ else if( sub_layer_profile_idc[i] == 2 || sub_layer_profile_compatibility_flag[i][2] ) {
+ bs_read_u(buf_info, 7);
+ bs_read_u(buf_info, 1);
+ bs_read_u(buf_info, 35);
+ }else
+ bs_read_u(buf_info, 43);
+ if( sub_layer_profile_idc[i] == 1 || sub_layer_profile_compatibility_flag[i][1] ||
+ sub_layer_profile_idc[i] == 2 || sub_layer_profile_compatibility_flag[i][2] ||
+ sub_layer_profile_idc[i] == 3 || sub_layer_profile_compatibility_flag[i][3] ||
+ sub_layer_profile_idc[i] == 4 || sub_layer_profile_compatibility_flag[i][4] ||
+ sub_layer_profile_idc[i] == 5 || sub_layer_profile_compatibility_flag[i][5] ||
+ sub_layer_profile_idc[i] == 9 || sub_layer_profile_compatibility_flag[i][9] ||
+ sub_layer_profile_idc[i] == 11|| sub_layer_profile_compatibility_flag[i][11])
+ bs_read_u(buf_info, 1);
+ else
+ bs_read_u(buf_info, 1);
+ }
+ if( sub_layer_level_present_flag[i] )
+ bs_read_u(buf_info, 8);
+ }
+}
+
+void
+hevc_parse_sequence_parameter_set(struct hevc_decode *dec, struct buffer_info *buf_info)
+{
+ uint32_t chroma_format_idc = 0;
+ uint32_t sps_max_sub_layers_minus1 = 0;
+
+ bs_read_u(buf_info, 4); /* sps_video_parameter_set_id */
+
+ sps_max_sub_layers_minus1 = bs_read_u(buf_info, 3); /* sps_max_sub_layers_minus1 */
+
+ bs_read_u(buf_info, 1); /* sps_temporal_id_nesting_flag */
+
+ profile_tier_level( 1, sps_max_sub_layers_minus1, buf_info);
+ bs_read_ue(buf_info);
+ chroma_format_idc = bs_read_ue(buf_info);
+ if(chroma_format_idc == 3)
+ bs_read_u(buf_info, 1); /* separate_colour_plane_flag */
+
+ dec->pic_width = bs_read_ue(buf_info);
+ dec->pic_height = bs_read_ue(buf_info);
+}
+
+void
+hevc_parse_pic_parameter_set(struct hevc_decode *dec, struct buffer_info *buf_info)
+{
+ bs_read_ue(buf_info); /* pps_pic_parameter_set_id */
+ bs_read_ue(buf_info); /* pps_seq_parameter_set_id */
+ dec->dependent_slice_segments_enabled_flag = bs_read_u(buf_info,1);
+ bs_read_u(buf_info,1);
+ dec->num_extra_slice_header_bits = bs_read_u(buf_info,3);
+}
+
+void
+hevc_slice_header(struct hevc_decode *dec, struct buffer_info *buf_info, uint8_t nal_unit_type)
+{
+ int i = 0;
+ uint32_t dependent_slice_segment_flag = 0;
+ uint32_t first_slice_segment_in_pic_flag = bs_read_u(buf_info, 1);
+ if(nal_unit_type >= HEVC_NAL_TYPE_BLA_W_LP && nal_unit_type <= HEVC_NAL_TYPE_RSV_IRAP_VCL23)
+ bs_read_u(buf_info, 1); /* no_output_of_prior_pics_flag */
+ bs_read_ue(buf_info); /* slice_pic_parameter_set_id */
+ if( !first_slice_segment_in_pic_flag ) {
+ if( dec->dependent_slice_segments_enabled_flag )
+ dependent_slice_segment_flag = bs_read_u(buf_info, 1);
+ bs_read_ue(buf_info); /* slice_segment_address */
+ }
+ if( !dependent_slice_segment_flag ) {
+ for( i = 0; i < dec->num_extra_slice_header_bits; i++ )
+ bs_read_u(buf_info, 1); /* slice_reserved_flag[ i ] */
+ dec->slice_type= bs_read_ue(buf_info);
+ }
+}
+
+uint8_t
+hevc_parse_nal(struct hevc_decode *dec, struct buffer_info *buf_info)
+{
+ uint8_t type = 0;
+
+ check_0s(buf_info, 1);
+ type = (uint8_t)bs_read_u(buf_info, 6);
+ dec->nal_unit_type = type;
+ bs_read_u(buf_info, 6);
+ bs_read_u(buf_info, 3);
+ switch (type) {
+ case HEVC_NAL_TYPE_NON_IDR_SLICE:
+ case HEVC_NAL_TYPE_IDR_SLICE:
+ case HEVC_NAL_TYEP_RADLN:
+ hevc_slice_header(dec, buf_info, dec->nal_unit_type);
+ break;
+ case HEVC_NAL_TYPE_SEQ_PARAM:
+ hevc_parse_sequence_parameter_set(dec, buf_info);
+ break;
+ case HEVC_NAL_TYPE_PIC_PARAM:
+ hevc_parse_pic_parameter_set(dec, buf_info);
+ break;
+ case HEVC_NAL_TYPE_ACCESS_UNIT:
+ case HEVC_NAL_TYPE_SEQ_EXTENSION:
+ case HEVC_NAL_TYPE_VID_PARAM:
+ /* NOP */
+ break;
+ default:
+ igt_info("Nal type unknown %d\n", type);
+ break;
+ }
+ return type;
+}
+
+
+void
+amdgpu_cs_vcn_hevc_enc_create(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context)
+{
+ int len, r;
+ uint32_t *p_task_size = NULL;
+ uint32_t task_offset = 0, st_offset;
+ uint32_t *st_size = NULL;
+ unsigned int width = 128, height = 64, buf_size;
+ uint32_t fw_maj = 1, fw_min = 9;
+
+ if (context->vcn_ip_version_major == 2) {
+ fw_maj = 1;
+ fw_min = 1;
+ } else if (context->vcn_ip_version_major == 3) {
+ fw_maj = 1;
+ fw_min = 0;
+ }
+
+ v_context->gWidth = width;
+ v_context->gHeight = height;
+ buf_size = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2;
+ v_context->enc_task_id = 1;
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &v_context->enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &v_context->cpb_buf, buf_size * 2, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = v_context->enc_buf.handle;
+ context->resources[context->num_resources++] = v_context->cpb_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ r = amdgpu_bo_cpu_map(v_context->enc_buf.handle, (void **)&v_context->enc_buf.ptr);
+ memset(v_context->enc_buf.ptr, 0, 128 * 1024);
+ r = amdgpu_bo_cpu_unmap(v_context->enc_buf.handle);
+
+ r = amdgpu_bo_cpu_map(v_context->cpb_buf.handle, (void **)&v_context->enc_buf.ptr);
+ memset(v_context->enc_buf.ptr, 0, buf_size * 2);
+ r = amdgpu_bo_cpu_unmap(v_context->cpb_buf.handle);
+
+ len = 0;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_head(v_context, context->ib_cpu, &len, true);
+
+ /* session info */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */
+ context->ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
+ context->ib_cpu[len++] = v_context->enc_buf.addr >> 32;
+ context->ib_cpu[len++] = v_context->enc_buf.addr;
+ context->ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE; */
+ *st_size = (len - st_offset) * 4;
+
+ /* task info */
+ task_offset = len;
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */
+ p_task_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = v_context->enc_task_id++; /* task_id */
+ context->ib_cpu[len++] = 0; /* feedback */
+ *st_size = (len - st_offset) * 4;
+
+ /* op init */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x01000001; /* RENCODE_IB_OP_INITIALIZE */
+ *st_size = (len - st_offset) * 4;
+
+ /* session_init */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000003; /* RENCODE_IB_PARAM_SESSION_INIT */
+
+ context->ib_cpu[len++] = RENCODE_ENCODE_STANDARD_HEVC;
+ context->ib_cpu[len++] = width;
+ context->ib_cpu[len++] = height;
+ context->ib_cpu[len++] = 0; /* padding width*/
+ context->ib_cpu[len++] = 0; /* padding height*/
+ context->ib_cpu[len++] = 0; /* pre encode mode */
+ context->ib_cpu[len++] = 0; /* chroma enabled : false */
+ context->ib_cpu[len++] = 0; /* slice_output_enabled = 0*/
+ context->ib_cpu[len++] = 0; /* session_init.display_remote = 0*/
+ *st_size = (len - st_offset) * 4;
+
+ /* slice control */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
+ context->ib_cpu[len++] = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
+ context->ib_cpu[len++] = RENCODE_HEVC_SLICE_NUM_CTBS_PER_SLICE;
+ context->ib_cpu[len++] = RENCODE_HEVC_SLICE_NUM_CTBS_PER_SLICE_SEGMENT;
+ context->ib_cpu[len++] = ALIGN(width, 16) / 16 * ALIGN(height, 16) / 16;
+ *st_size = (len - st_offset) * 4;
+
+ /* inloop filter */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
+ context->ib_cpu[len++] = 0; /* hevc_deblock.loop_filter_across_slices_enabled */
+ context->ib_cpu[len++] = 0; /* hevc_deblock.deblocking_filter_disabled */
+ context->ib_cpu[len++] = 0; /* hevc_deblock.beta_offset_div2 */
+ context->ib_cpu[len++] = 0; /* hevc_deblock.tc_offset_div2 */
+ context->ib_cpu[len++] = 0; /* hevc_deblock.cb_qp_offset */
+ context->ib_cpu[len++] = 0; /* hevc_deblock.cr_qp_offset */
+ context->ib_cpu[len++] = 1; /* !sample_adaptive_offset_enabled_flag */
+ *st_size = (len - st_offset) * 4;
+
+ /* layer control */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000004; /* RENCODE_IB_PARAM_LAYER_CONTROL */
+ context->ib_cpu[len++] = 1; /* max temporal layer */
+ context->ib_cpu[len++] = 1; /* no of temporal layer */
+ *st_size = (len - st_offset) * 4;
+
+ /* rc_session init */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000006; /* RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT */
+ context->ib_cpu[len++] = 0; /* rate control */
+ context->ib_cpu[len++] = 48; /* vbv buffer level */
+ *st_size = (len - st_offset) * 4;
+
+ /* quality params */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000009; /* RENCODE_IB_PARAM_QUALITY_PARAMS */
+ context->ib_cpu[len++] = 0; /* vbaq mode */
+ context->ib_cpu[len++] = 0; /* scene change sensitivity */
+ context->ib_cpu[len++] = 0; /* scene change min idr interval */
+ context->ib_cpu[len++] = 0; /* two_pass_search_center_map_mode*/
+ if (context->vcn_ip_version_major >= 3)
+ context->ib_cpu[len++] = 0;
+ *st_size = (len - st_offset) * 4;
+
+ /* layer select */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000005; /* RENCODE_IB_PARAM_LAYER_SELECT */
+ context->ib_cpu[len++] = 0; /* temporal layer */
+ *st_size = (len - st_offset) * 4;
+
+ /* rc layer init */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000007; /* RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT */
+ context->ib_cpu[len++] = 0;
+ context->ib_cpu[len++] = 0;
+ context->ib_cpu[len++] = 25;
+ context->ib_cpu[len++] = 1;
+ context->ib_cpu[len++] = 0x01312d00;
+ context->ib_cpu[len++] = 0;
+ context->ib_cpu[len++] = 0;
+ context->ib_cpu[len++] = 0;
+ *st_size = (len - st_offset) * 4;
+
+ /* layer select */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000005; /* RENCODE_IB_PARAM_LAYER_SELECT */
+ context->ib_cpu[len++] = 0; /* temporal layer */
+ *st_size = (len - st_offset) * 4;
+
+ /* rc per pic */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000008; /* RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE */
+ context->ib_cpu[len++] = 25; /* enc_pic.rc_per_pic.qp */
+ context->ib_cpu[len++] = 0; /* enc_pic.rc_per_pic.min_qp_app */
+ context->ib_cpu[len++] = 51; /* enc_pic.rc_per_pic.max_qp_app */
+ context->ib_cpu[len++] = 0; /* enc_pic.rc_per_pic.max_au_size */
+ context->ib_cpu[len++] = 1; /* enc_pic.rc_per_pic.enabled_filler_data */
+ context->ib_cpu[len++] = 0; /* enc_pic.rc_per_pic.skip_frame_enable */
+ context->ib_cpu[len++] = 1; /* enc_pic.rc_per_pic.enforce_hrd */
+ /*context->ib_cpu[len++] = 0;*/
+ *st_size = (len - st_offset) * 4;
+
+ /* op init rc */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x01000004; /* RENCODE_IB_OP_INIT_RC */
+ *st_size = (len - st_offset) * 4;
+
+ /* op init rc vbv */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x01000005; /* RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL */
+ *st_size = (len - st_offset) * 4;
+
+ *p_task_size = (len - task_offset) * 4;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+
+ r = submit(device_handle, context, len, AMDGPU_HW_IP_VCN_ENC);
+ igt_assert_eq(r, 0);
+
+}
+
+void
+amdgpu_cs_vcn_hevc_enc_encode_frame(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context,
+ int frame_type)
+{
+ struct amdgpu_mmd_bo bs_buf, fb_buf, input_buf;
+ int len, r, i;
+ unsigned int width = 128, height = 64, buf_size;
+ uint32_t *p_task_size = NULL;
+ uint32_t task_offset = 0, st_offset;
+ uint32_t *st_size = NULL;
+ uint32_t fw_maj = 1, fw_min = 9;
+
+ if (context->vcn_ip_version_major == 2) {
+ fw_maj = 1;
+ fw_min = 1;
+ } else if (context->vcn_ip_version_major == 3) {
+ fw_maj = 1;
+ fw_min = 0;
+ }
+ v_context->gSliceType = frame_type;
+ buf_size = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2;
+
+ context->num_resources = 0;
+ alloc_resource(device_handle, &bs_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &fb_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
+ alloc_resource(device_handle, &input_buf, buf_size, AMDGPU_GEM_DOMAIN_GTT);
+ context->resources[context->num_resources++] = v_context->enc_buf.handle;
+ context->resources[context->num_resources++] = v_context->cpb_buf.handle;
+ context->resources[context->num_resources++] = bs_buf.handle;
+ context->resources[context->num_resources++] = fb_buf.handle;
+ context->resources[context->num_resources++] = input_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+
+
+ r = amdgpu_bo_cpu_map(bs_buf.handle, (void **)&bs_buf.ptr);
+ memset(bs_buf.ptr, 0, 4096);
+ r = amdgpu_bo_cpu_unmap(bs_buf.handle);
+
+ r = amdgpu_bo_cpu_map(fb_buf.handle, (void **)&fb_buf.ptr);
+ memset(fb_buf.ptr, 0, 4096);
+ r = amdgpu_bo_cpu_unmap(fb_buf.handle);
+
+ r = amdgpu_bo_cpu_map(input_buf.handle, (void **)&input_buf.ptr);
+ igt_assert_eq(r, 0);
+ for (i = 0; i < ALIGN(height, 32) * 3 / 2; i++)
+ memcpy(input_buf.ptr + i * ALIGN(width, 256), frame_128_64 + i * width, width);
+
+ r = amdgpu_bo_cpu_unmap(input_buf.handle);
+ igt_assert_eq(r, 0);
+
+ len = 0;
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_head(v_context, context->ib_cpu, &len, true);
+
+ /* session info */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */
+ context->ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
+ context->ib_cpu[len++] = v_context->enc_buf.addr >> 32;
+ context->ib_cpu[len++] = v_context->enc_buf.addr;
+ context->ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE */;
+ *st_size = (len - st_offset) * 4;
+
+ /* task info */
+ task_offset = len;
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */
+ p_task_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = v_context->enc_task_id++; /* task_id */
+ context->ib_cpu[len++] = 1; /* feedback */
+ *st_size = (len - st_offset) * 4;
+
+ if (frame_type == 2) {
+
+ /* aud */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn */
+ context->ib_cpu[len++] = 0x00000000; /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD; */
+ context->ib_cpu[len++] = 0x00000007; /* aud len */
+ context->ib_cpu[len++] = 0x00000001; /* start code */
+ context->ib_cpu[len++] = 0x46011000;
+
+ *st_size = (len - st_offset) * 4;
+
+ /* vps */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn */
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS; */
+ context->ib_cpu[len++] = 0x0000001b; /* vps len */
+ context->ib_cpu[len++] = 0x00000001; /* start code */
+ context->ib_cpu[len++] = 0x40010C01;
+ context->ib_cpu[len++] = 0xFFFF0160;
+ context->ib_cpu[len++] = 0x00000300;
+ context->ib_cpu[len++] = 0xB0000003;
+ context->ib_cpu[len++] = 0x00000300;
+ context->ib_cpu[len++] = 0x1E2C0900;
+
+ *st_size = (len - st_offset) * 4;
+
+ /* pps */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1*/
+ else
+ context->ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn*/
+ context->ib_cpu[len++] = 0x00000003; /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS */
+ context->ib_cpu[len++] = 0x0000000b; /* pps len */
+ context->ib_cpu[len++] = 0x00000001; /* start code */
+ context->ib_cpu[len++] = 0x4401E0F5;
+ context->ib_cpu[len++] = 0x80992000;
+ *st_size = (len - st_offset) * 4;
+
+ /* sps */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn */
+ context->ib_cpu[len++] = 0x00000002; /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS */
+ context->ib_cpu[len++] = 0x0000002D; /* sps len */
+ context->ib_cpu[len++] = 0x00000001; /* start code */
+ context->ib_cpu[len++] = 0x42010101;
+ context->ib_cpu[len++] = 0x60000003;
+ context->ib_cpu[len++] = 0x00B00000;
+ context->ib_cpu[len++] = 0x03000003;
+ context->ib_cpu[len++] = 0x001EA010;
+ context->ib_cpu[len++] = 0x204172e4;
+ context->ib_cpu[len++] = 0x90a544b8;
+ context->ib_cpu[len++] = 0x9a020000;
+ context->ib_cpu[len++] = 0x03000200;
+ context->ib_cpu[len++] = 0x00030032;
+ context->ib_cpu[len++] = 0x10000000;
+
+ *st_size = (len - st_offset) * 4;
+ }
+ /* slice header */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 2,3 */
+ if (frame_type == 2) {
+ context->ib_cpu[len++] = 0x26010000;
+ /*context->ib_cpu[len++] = 0x501b0000;*/
+ context->ib_cpu[len++] = 0x40000000;
+ } else {
+ context->ib_cpu[len++] = 0x41000000;
+ context->ib_cpu[len++] = 0x34210000;
+ }
+ context->ib_cpu[len++] = 0x60000000;
+ amdgpu_cs_vcn_ib_zero_count(context, &len, 13);
+
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_HEADER_INSTRUCTION_COPY */
+ context->ib_cpu[len++] = 0x00000010;
+ context->ib_cpu[len++] = 0x00010001; /* RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE */
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_HEADER_INSTRUCTION_COPY */
+ context->ib_cpu[len++] = 0x00000002; /* RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE */
+ context->ib_cpu[len++] = 0x00010002; /* RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA */
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00010000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000001;
+ context->ib_cpu[len++] = 0x00000003;
+ context->ib_cpu[len++] = 0x00010003;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000001;
+ amdgpu_cs_vcn_ib_zero_count(context, &len, 17);
+
+ *st_size = (len - st_offset) * 4;
+
+ /* encode params */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 1*/
+ else
+ context->ib_cpu[len++] = 0x0000000f; /* RENCODE_IB_PARAM_ENCODE_PARAMS other vcn*/
+ context->ib_cpu[len++] = frame_type;
+ context->ib_cpu[len++] = 0x0001f000;
+ context->ib_cpu[len++] = input_buf.addr >> 32;
+ context->ib_cpu[len++] = input_buf.addr;
+ context->ib_cpu[len++] = (input_buf.addr + ALIGN(width, 256) * ALIGN(height, 32)) >> 32;
+ context->ib_cpu[len++] = input_buf.addr + ALIGN(width, 256) * ALIGN(height, 32);
+ context->ib_cpu[len++] = 0x00000100;
+ context->ib_cpu[len++] = 0x00000080;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0xffffffff;
+ context->ib_cpu[len++] = 0x00000000;
+ *st_size = (len - st_offset) * 4;
+
+ /* encode context */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x0000000d; /* ENCODE_CONTEXT_BUFFER vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x00000011; /* ENCODE_CONTEXT_BUFFER other vcn*/
+ context->ib_cpu[len++] = v_context->cpb_buf.addr >> 32;
+ context->ib_cpu[len++] = v_context->cpb_buf.addr;
+ context->ib_cpu[len++] = 0x00000002; /* swizzle mode */
+ context->ib_cpu[len++] = 0x00000100; /* luma pitch */
+ context->ib_cpu[len++] = 0x00000100; /* chroma pitch */
+ context->ib_cpu[len++] = 0x00000010; /* num_reconstructed_pictures */
+ context->ib_cpu[len++] = 0x00000000; /* luma_offset,chroma_offset,unused_offset1,unused_offset2 for RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES (34) */
+ context->ib_cpu[len++] = 0x00010000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00018000;
+ context->ib_cpu[len++] = 0x00028000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00030000;
+ context->ib_cpu[len++] = 0x00040000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00048000;
+ context->ib_cpu[len++] = 0x00058000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00060000;
+ context->ib_cpu[len++] = 0x00070000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00078000;
+ context->ib_cpu[len++] = 0x00088000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00090000;
+ context->ib_cpu[len++] = 0x000a0000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x000a8000;
+ context->ib_cpu[len++] = 0x000b8000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x000c0000;
+ context->ib_cpu[len++] = 0x000d0000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x000d8000;
+ context->ib_cpu[len++] = 0x000e8000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x000f0000;
+ context->ib_cpu[len++] = 0x00100000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00108000;
+ context->ib_cpu[len++] = 0x00118000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00120000;
+ context->ib_cpu[len++] = 0x00130000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00138000;
+ context->ib_cpu[len++] = 0x00148000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00150000;
+ context->ib_cpu[len++] = 0x00160000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00168000;
+ context->ib_cpu[len++] = 0x00178000;
+ amdgpu_cs_vcn_ib_zero_count(context, &len, 74);
+ context->ib_cpu[len++] = 0x00000100; /* pre_encode_picture_luma_pitch */
+ context->ib_cpu[len++] = 0x00000100; /* pre_encode_picture_chroma_pitch */
+ amdgpu_cs_vcn_ib_zero_count(context, &len, 136);
+ context->ib_cpu[len++] = 0x00000000; /* pre_encode_input_picture.rgb.red_offset */
+ context->ib_cpu[len++] = 0x00000000; /* pre_encode_input_picture.rgb.green_offset */
+ context->ib_cpu[len++] = 0x00000000; /* pre_encode_input_picture.rgb.blue_offset */
+ context->ib_cpu[len++] = 0x00000000; /* two_pass_search_center_map_offset */
+ context->ib_cpu[len++] = 0x00000000; /* colloc_buffer_offset */
+ *st_size = (len - st_offset) * 4;
+
+ /* bitstream buffer */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x0000000e; /* VIDEO_BITSTREAM_BUFFER vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x00000012; /* VIDEO_BITSTREAM_BUFFER other vcn */
+ context->ib_cpu[len++] = 0x0000000; /* mode */
+ context->ib_cpu[len++] = bs_buf.addr >> 32;
+ context->ib_cpu[len++] = bs_buf.addr;
+ context->ib_cpu[len++] = 0x0001f000;
+ context->ib_cpu[len++] = 0x00000000;
+ *st_size = (len - st_offset) * 4;
+
+ /* feedback */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x00000010; /* FEEDBACK_BUFFER vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x00000015; /* FEEDBACK_BUFFER vcn 2,3 */
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = fb_buf.addr >> 32;
+ context->ib_cpu[len++] = fb_buf.addr;
+ context->ib_cpu[len++] = 0x00000010;
+ context->ib_cpu[len++] = 0x00000028;
+ *st_size = (len - st_offset) * 4;
+
+ /* intra refresh */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ if (context->vcn_ip_version_major == 1)
+ context->ib_cpu[len++] = 0x0000000c; /* INTRA_REFRESH vcn 1 */
+ else
+ context->ib_cpu[len++] = 0x00000010; /* INTRA_REFRESH vcn 2,3 */
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ *st_size = (len - st_offset) * 4;
+
+ if (context->vcn_ip_version_major != 1) {
+ /* Input Format */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = 0x0000000c;
+ context->ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_VOLUME_G22_BT709 */
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000001;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_BIT_DEPTH_8_BIT */
+ context->ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_PACKING_FORMAT_NV12 */
+ *st_size = (len - st_offset) * 4;
+
+ /* Output Format */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = 0x0000000d;
+ context->ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_VOLUME_G22_BT709 */
+ context->ib_cpu[len++] = 0x00000001;
+ context->ib_cpu[len++] = 0x00000000;
+ context->ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_BIT_DEPTH_8_BIT */
+ *st_size = (len - st_offset) * 4;
+ }
+
+ /* op_speed */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = 0x01000006; /* SPEED_ENCODING_MODE */
+ *st_size = (len - st_offset) * 4;
+ /* op_enc */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = 0x01000003;
+ *st_size = (len - st_offset) * 4;
+
+ *p_task_size = (len - task_offset) * 4;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+
+ r = submit(device_handle, context, len, AMDGPU_HW_IP_VCN_ENC);
+ igt_assert_eq(r, 0);
+
+ /* check result */
+ check_result(v_context, fb_buf, bs_buf, frame_type, IGT_CODEC_TYPE_HEVC);
+
+ free_resource(&fb_buf);
+ free_resource(&bs_buf);
+ free_resource(&input_buf);
+}
+
+void
+amdgpu_cs_vcn_hevc_enc_encode(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context)
+{
+ amdgpu_cs_vcn_hevc_enc_encode_frame(device_handle, context, v_context, 2); /* IDR frame */
+}
+
+void
+amdgpu_cs_vcn_hevc_enc_destroy(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context)
+{
+ int len = 0, r;
+ uint32_t *p_task_size = NULL;
+ uint32_t task_offset = 0, st_offset;
+ uint32_t *st_size = NULL;
+ uint32_t fw_maj = 1, fw_min = 9;
+
+ if (context->vcn_ip_version_major == 2) {
+ fw_maj = 1;
+ fw_min = 1;
+ } else if (context->vcn_ip_version_major == 3) {
+ fw_maj = 1;
+ fw_min = 0;
+ }
+
+ context->num_resources = 0;
+ context->resources[context->num_resources++] = v_context->enc_buf.handle;
+ context->resources[context->num_resources++] = context->ib_handle;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_head(v_context, context->ib_cpu, &len, true);
+
+ /* session info */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */
+ context->ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0));
+ context->ib_cpu[len++] = v_context->enc_buf.addr >> 32;
+ context->ib_cpu[len++] = v_context->enc_buf.addr;
+ context->ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE; */
+ *st_size = (len - st_offset) * 4;
+
+ /* task info */
+ task_offset = len;
+ st_offset = len;
+ st_size = &context->ib_cpu[len++]; /* size */
+ context->ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */
+ p_task_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = v_context->enc_task_id++; /* task_id */
+ context->ib_cpu[len++] = 0; /* feedback */
+ *st_size = (len - st_offset) * 4;
+
+ /* op close */
+ st_offset = len;
+ st_size = &context->ib_cpu[len++];
+ context->ib_cpu[len++] = 0x01000002; /* RENCODE_IB_OP_CLOSE_SESSION */
+ *st_size = (len - st_offset) * 4;
+
+ *p_task_size = (len - task_offset) * 4;
+
+ if (context->vcn_unified_ring)
+ amdgpu_cs_sq_ib_tail(v_context, context->ib_cpu + len);
+
+ r = submit(device_handle, context, len, AMDGPU_HW_IP_VCN_ENC);
+ igt_assert_eq(r, 0);
+
+ free_resource(&v_context->cpb_buf);
+ free_resource(&v_context->enc_buf);
+}
diff --git a/tests/amdgpu/amd_vcn_hevc.h b/tests/amdgpu/amd_vcn_hevc.h
new file mode 100644
index 000000000..e185ae320
--- /dev/null
+++ b/tests/amdgpu/amd_vcn_hevc.h
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ */
+
+#define HEVC_NAL_TYPE_NON_IDR_SLICE 1
+#define HEVC_NAL_TYPE_DP_A_SLICE 2
+#define HEVC_NAL_TYPE_DP_B_SLICE 3
+#define HEVC_NAL_TYPE_DP_C_SLICE 0x4
+#define HEVC_NAL_TYPE_IDR_SLICE 0x13
+/*#define HEVC_NAL_TYPE_SEI 0x6*/
+#define HEVC_NAL_TYEP_RADLN 0x6
+#define HEVC_NAL_TYPE_VID_PARAM 0x20
+#define HEVC_NAL_TYPE_SEQ_PARAM 0x21
+#define HEVC_NAL_TYPE_PIC_PARAM 0x22
+#define HEVC_NAL_TYPE_ACCESS_UNIT 0x23
+#define HEVC_NAL_TYPE_END_OF_SEQ 0x24
+#define HEVC_NAL_TYPE_END_OF_STREAM 025
+#define HEVC_NAL_TYPE_FILLER_DATA 0x26
+#define HEVC_NAL_TYPE_SEQ_EXTENSION 0x27
+#define HEVC_NAL_TYPE_BLA_W_LP 0x10
+#define HEVC_NAL_TYPE_RSV_IRAP_VCL23 0x17
+
+#define HEVC_START_CODE 0x000001
+
+#define RENCODE_ENCODE_STANDARD_HEVC 0
+#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
+#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
+#define RENCODE_HEVC_SLICE_NUM_CTBS_PER_SLICE 0x00000008
+#define RENCODE_HEVC_SLICE_NUM_CTBS_PER_SLICE_SEGMENT 0x00000008
+#define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
+#define RENCODE_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
+
+void
+vcn_hevc_dec_cmd(struct mmd_context *context, struct vcn_context *v_context,
+ uint64_t addr, unsigned int cmd, int *idx);
+
+;
+void
+amdgpu_cs_vcn_hevc_dec_destroy(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context);
+
+void
+check_hevc_result(struct vcn_context *v_context, struct amdgpu_mmd_bo fb_buf,
+ struct amdgpu_mmd_bo bs_buf, int frame_type);
+
+
+void
+hevc_parse_sequence_parameter_set(struct hevc_decode *dec, struct buffer_info *buf_info);
+
+void
+hevc_slice_header(struct hevc_decode *dec, struct buffer_info *buf_info, uint8_t nal_unit_type);
+
+uint8_t
+hevc_parse_nal(struct hevc_decode *dec, struct buffer_info *buf_info);
+
+uint32_t
+hevc_find_next_start_code(uint8_t *pBuf, uint32_t bufLen);
+
+int
+verify_hevc_checksum(struct vcn_context *v_context, uint8_t *buffer, uint32_t buffer_size);
+
+void
+amdgpu_cs_vcn_hevc_dec_create(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context);
+
+void
+amdgpu_cs_vcn_hevc_dec_decode(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context);
+
+void
+amdgpu_cs_vcn_hevc_enc_create(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context);
+
+void
+amdgpu_cs_vcn_hevc_enc_encode_frame(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context,
+ int frame_type);
+
+void
+amdgpu_cs_vcn_hevc_enc_encode(amdgpu_device_handle device_handle,
+ struct mmd_context *context, struct vcn_context *v_context);
+
+void
+amdgpu_cs_vcn_hevc_enc_destroy(amdgpu_device_handle device_handle, struct mmd_context *context,
+ struct vcn_context *v_context);
+void
+hevc_parse_pic_parameter_set(struct hevc_decode *dec, struct buffer_info *buf_info);
--
2.34.1
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