[PATCH i-g-t, v2] tests/intel/xe_vm: Fix WB caching PAT index for coherency mode

[Kamil Konieczny]

Hi Jagmeet,
On 2024-03-26 at 11:16:28 -0700, Jagmeet Randhawa wrote:
> Ensure we set a suitable default pat_index, which is always compatible
> with any CPU caching mode, like intel_get_pat_idx_wb(). For example,
> currently we are blindly selecting pat_index=0 which has COH_NONE on LNL
> and then attempting to use that with CPU caching mode WB, which is not
> supported by the KMD.
> 

You got also r-b from Oak, so:
Reviewed-by: Oak Zeng <oak.zeng at intel.com>

Please also look at his reply regarding commit description.

Regards,
Kamil

> Reviewed-by: Matthew Auld <matthew.auld at intel.com>
> Signed-off-by: Jagmeet Randhawa <jagmeet.randhawa at intel.com>
> ---
>  tests/intel/xe_vm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> index 7c061c497..1f458174d 100644
> --- a/tests/intel/xe_vm.c
> +++ b/tests/intel/xe_vm.c
> @@ -1789,6 +1789,7 @@ static void bind_flag_invalid(int fd)
>  	bind.bind.range = bo_size;
>  	bind.bind.addr = addr;
>  	bind.bind.op = DRM_XE_VM_BIND_OP_MAP;
> +	bind.bind.pat_index = intel_get_pat_idx_wb(fd);
>  	bind.num_syncs = 1;
>  	bind.syncs = (uintptr_t)sync;
>  
> -- 
> 2.25.1
>