[PATCH i-g-t] tests/intel/kms_pm_dc: Add a new test to validate the deep sleep state during extended vblank
Jeevan B
jeevan.b at intel.com
Mon May 27 04:19:08 UTC 2024
Add a new test to validate deep sleep states during extended vblank
scenarios, where two frames are committed simultaneously for a give
time with reduced refresh rate.
v2: dealy of one frame added to simulate extended vblank.
remove vrr related debug checks.
Signed-off-by: Jeevan B <jeevan.b at intel.com>
---
tests/intel/kms_pm_dc.c | 49 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 7766d34d7..9f89e537d 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -584,6 +584,46 @@ static unsigned int read_pkgc_counter(int debugfs_root_fd)
return get_dc_counter(str);
}
+static void test_deep_pkgc_state(data_t *data)
+{
+ unsigned int pre_val = 0, cur_val = 0;
+ time_t start = time(NULL), duration = 2, delay;
+ enum pipe pipe;
+ bool pkgc_flag;
+ igt_display_t *display = &data->display;
+ igt_plane_t *primary;
+ igt_output_t *output;
+
+ for_each_pipe_with_valid_output(display, pipe, output) {
+ igt_output_set_pipe(output, pipe);
+ data->output = output;
+ data->mode = igt_output_get_mode(output);
+ setup_videoplayback(data);
+ igt_require(igt_output_has_prop(output, IGT_CONNECTOR_VRR_CAPABLE));
+ igt_require(igt_output_get_prop(output, IGT_CONNECTOR_VRR_CAPABLE));
+
+ primary = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_PRIMARY);
+ pre_val = read_pkgc_counter(data->debugfs_root_fd);
+ delay = 1 * ((1000 * 1000) / data->mode->vrefresh);
+ while (time(NULL) - start < duration) {
+ igt_plane_set_fb(primary, &data->fb_rgb);
+ igt_display_commit(&data->display);
+ usleep(delay);
+
+ igt_plane_set_fb(primary, &data->fb_rgr);
+ igt_display_commit(&data->display);
+ cur_val = read_pkgc_counter(data->debugfs_root_fd);
+ if (cur_val > pre_val) {
+ pkgc_flag = true;
+ continue;
+ }
+ }
+ }
+ cleanup_dc3co_fbs(data);
+ igt_assert_f(pkgc_flag, "PKGC10 is not achieved.\n");
+}
+
static void test_pkgc_state_dpms(data_t *data)
{
unsigned int timeout_sec = 6;
@@ -687,6 +727,15 @@ igt_main
test_dc_state_psr(&data, CHECK_DC6);
}
+ igt_describe("This test validates display engine entry to DC8 state "
+ "while extended vblank");
+ igt_subtest("deep-pkgc") {
+ igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
+ "PC8+ residencies not supported\n");
+ igt_require(intel_display_ver(data.devid) >= 20);
+ test_deep_pkgc_state(&data);
+ }
+
igt_describe("This test validates display engine entry to DC5 state "
"while all connectors's DPMS property set to OFF");
igt_subtest("dc5-dpms") {
--
2.25.1
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