[PATCH v2] tests/xe_exec_sip: skip invalid instruction in SIP routine
Zbigniew Kempczyński
zbigniew.kempczynski at intel.com
Fri Oct 11 06:39:07 UTC 2024
On Thu, Oct 10, 2024 at 05:59:27PM +0200, Andrzej Hajda wrote:
> Exception handler (SIP) should skip invalid instruction,
> ie after return from SIP IP should point to the next instruction.
> Otherwise we risk undefined behavior.
>
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2977
> Signed-off-by: Andrzej Hajda <andrzej.hajda at intel.com>
Great, looks good to me.
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
--
Zbigniew
> ---
> v2: resend due to malformed RCPT list.
> ---
> lib/gpgpu_shader.c | 14 ++++++++++++++
> lib/gpgpu_shader.h | 1 +
> lib/iga64_generated_codes.c | 39 +++++++++++++++++++++++++++++++--------
> tests/intel/xe_exec_sip.c | 2 ++
> 4 files changed, 48 insertions(+), 8 deletions(-)
>
> diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
> index e88870bbb675..4e1b8d5e9009 100644
> --- a/lib/gpgpu_shader.c
> +++ b/lib/gpgpu_shader.c
> @@ -593,6 +593,20 @@ void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset)
> ", y_offset);
> }
>
> +/**
> + * gpgpu_shader__increase_aip:
> + * @shdr: shader to be modified
> + * @value: value to be added to AIP register
> + *
> + * Increase AIP by @value. Useful in SIP to skip instruction causing exception.
> + */
> +void gpgpu_shader__increase_aip(struct gpgpu_shader *shdr, uint32_t value)
> +{
> + emit_iga64_code(shdr, write_aip, " \n\
> +(W) add (1|M0) cr0.2:ud cr0.2:ud ARG(0):ud \n\
> + ", value);
> +}
> +
> /**
> * gpgpu_shader__write_dword:
> * @shdr: shader to be modified
> diff --git a/lib/gpgpu_shader.h b/lib/gpgpu_shader.h
> index 5f6260fb3a8f..c7c21c115c71 100644
> --- a/lib/gpgpu_shader.h
> +++ b/lib/gpgpu_shader.h
> @@ -80,6 +80,7 @@ void gpgpu_shader__end_system_routine_step_if_eq(struct gpgpu_shader *shdr,
> uint32_t dw_offset,
> uint32_t value);
> void gpgpu_shader__write_aip(struct gpgpu_shader *shdr, uint32_t y_offset);
> +void gpgpu_shader__increase_aip(struct gpgpu_shader *shdr, uint32_t value);
> void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
> uint32_t y_offset);
> void gpgpu_shader__write_on_exception(struct gpgpu_shader *shdr, uint32_t dw, uint32_t x_offset,
> diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
> index 9f0be5cd336e..6638be07b356 100644
> --- a/lib/iga64_generated_codes.c
> +++ b/lib/iga64_generated_codes.c
> @@ -3,7 +3,7 @@
>
> #include "gpgpu_shader.h"
>
> -#define MD5_SUM_IGA64_ASMS 8a479a91a5152263281914a99be4f4d4
> +#define MD5_SUM_IGA64_ASMS ec9d477415eebb7d6983395f1bcde78f
>
> struct iga64_template const iga64_code_gpgpu_fill[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> @@ -204,7 +204,7 @@ struct iga64_template const iga64_code_write_on_exception[] = {
> 0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
> 0x80000961, 0x30014220, 0x00000000, 0x00000000,
> 0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
> - 0x84134031, 0x00000000, 0xd00e0494, 0x04000000,
> + 0x84132031, 0x00000000, 0xd00e0494, 0x04000000,
> 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> @@ -220,7 +220,7 @@ struct iga64_template const iga64_code_write_on_exception[] = {
> 0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
> 0x80000961, 0x30014220, 0x00000000, 0x00000000,
> 0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
> - 0x80001a01, 0x00010000, 0x00000000, 0x00000000,
> + 0x80001901, 0x00010000, 0x00000000, 0x00000000,
> 0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
> 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> @@ -237,7 +237,7 @@ struct iga64_template const iga64_code_write_on_exception[] = {
> 0x80000965, 0x03058220, 0x02008010, 0xc0ded005,
> 0x80000961, 0x30014220, 0x00000000, 0x00000000,
> 0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
> - 0x84134031, 0x00000000, 0xc0000414, 0x02a00000,
> + 0x84132031, 0x00000000, 0xc0000414, 0x02a00000,
> 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> @@ -253,7 +253,7 @@ struct iga64_template const iga64_code_write_on_exception[] = {
> 0x80000965, 0x03058220, 0x02008020, 0xc0ded005,
> 0x80000961, 0x30014220, 0x00000000, 0x00000000,
> 0x80001a70, 0x00018220, 0x12000304, 0xc0ded006,
> - 0x80001a01, 0x00010000, 0x00000000, 0x00000000,
> + 0x80001901, 0x00010000, 0x00000000, 0x00000000,
> 0x81044031, 0x00000000, 0xc0000414, 0x02a00000,
> 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> @@ -270,7 +270,7 @@ struct iga64_template const iga64_code_write_on_exception[] = {
> 0x80000165, 0x03058220, 0x02008020, 0xc0ded005,
> 0x80000161, 0x30014220, 0x00000000, 0x00000000,
> 0x80000270, 0x00018220, 0x12000304, 0xc0ded006,
> - 0x8104a031, 0x00000000, 0xc0000414, 0x02a00000,
> + 0x81049031, 0x00000000, 0xc0000414, 0x02a00000,
> 0x80000001, 0x00010000, 0x20000000, 0x00000000,
> 0x80000001, 0x00010000, 0x30000000, 0x00000000,
> 0x80000101, 0x00010000, 0x00000000, 0x00000000,
> @@ -408,6 +408,29 @@ struct iga64_template const iga64_code_media_block_write[] = {
> }}
> };
>
> +struct iga64_template const iga64_code_write_aip[] = {
> + { .gen_ver = 2000, .size = 8, .code = (const uint32_t []) {
> + 0x80000940, 0x80218220, 0x02008020, 0xc0ded000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1270, .size = 8, .code = (const uint32_t []) {
> + 0x80000940, 0x80418220, 0x02008040, 0xc0ded000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1260, .size = 8, .code = (const uint32_t []) {
> + 0x80000940, 0x80218220, 0x02008020, 0xc0ded000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 1250, .size = 8, .code = (const uint32_t []) {
> + 0x80000940, 0x80418220, 0x02008040, 0xc0ded000,
> + 0x80000901, 0x00010000, 0x00000000, 0x00000000,
> + }},
> + { .gen_ver = 0, .size = 8, .code = (const uint32_t []) {
> + 0x80000140, 0x80418220, 0x02008040, 0xc0ded000,
> + 0x80000101, 0x00010000, 0x00000000, 0x00000000,
> + }}
> +};
> +
> struct iga64_template const iga64_code_media_block_write_aip[] = {
> { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
> 0x80000961, 0x05050220, 0x00008020, 0x00000000,
> @@ -586,7 +609,7 @@ struct iga64_template const iga64_code_inc_r40_jump_neq[] = {
> 0x80000040, 0x28058220, 0x02002804, 0x00000001,
> 0x80000061, 0x30014220, 0x00000000, 0x00000000,
> 0x80000270, 0x00018220, 0x22002804, 0xc0ded000,
> - 0x81000020, 0x00004000, 0x00000000, 0xffffffd0,
> + 0x81000120, 0x00004000, 0x00000000, 0xffffffd0,
> 0x80000101, 0x00010000, 0x00000000, 0x00000000,
> }}
> };
> @@ -656,7 +679,7 @@ struct iga64_template const iga64_code_jump_dw_neq[] = {
> 0x80049031, 0x1f0c0000, 0xc0001e0c, 0x02400000,
> 0x80000061, 0x30014220, 0x00000000, 0x00000000,
> 0x80002070, 0x00018220, 0x22001f04, 0xc0ded001,
> - 0x81000020, 0x00004000, 0x00000000, 0xffffff90,
> + 0x81000120, 0x00004000, 0x00000000, 0xffffff90,
> 0x80000101, 0x00010000, 0x00000000, 0x00000000,
> }}
> };
> diff --git a/tests/intel/xe_exec_sip.c b/tests/intel/xe_exec_sip.c
> index 2294468c2983..de33bdf2dd0f 100644
> --- a/tests/intel/xe_exec_sip.c
> +++ b/tests/intel/xe_exec_sip.c
> @@ -126,6 +126,8 @@ static struct gpgpu_shader *get_sip(int fd, enum sip_type sip_type, unsigned int
> case SIP_INV_INSTR:
> gpgpu_shader__write_on_exception(sip, SIP_CANARY2, 0, y_offset,
> ILLEGAL_OPCODE_STATUS, 0);
> + /* skip invalid instruction */
> + gpgpu_shader__increase_aip(sip, 16);
> break;
> default:
> break;
>
> ---
> base-commit: cc3fa4e36bb0445565f40f989540b9deacb92e12
> change-id: 20241010-skip_invalid_instruction-1ea5b45a0834
>
> Best regards,
> --
> Andrzej Hajda <andrzej.hajda at intel.com>
>
More information about the igt-dev
mailing list