[PATCH i-g-t v2 2/2] lib/amdgpu: Implement priority and secure flags for user queues

[Khatri, Sunil]

[AMD Official Use Only - AMD Internal Distribution Only]

-----Original Message-----
From: Jesse.zhang at amd.com <jesse.zhang at amd.com>
Sent: Thursday, April 17, 2025 2:23 PM
To: igt-dev at lists.freedesktop.org
Cc: Prosyak, Vitaly <Vitaly.Prosyak at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Khatri, Sunil <Sunil.Khatri at amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang at amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang at amd.com>
Subject: [PATCH i-g-t v2 2/2] lib/amdgpu: Implement priority and secure flags for user queues

This patch adds support for queue priority levels and secure queue creation flags in the user queue interface. The changes include:

1. Extended the amdgpu_ring_context struct to store queue priority

2. Modified amdgpu_user_queue_create() to:
   - Parse and pass through priority flags from context
   - Handle secure queue flag
   - Include flags in queue creation IOCTL calls

The priority levels allow workloads to specify different scheduling priorities, with HIGH priority restricted to admin-only use. The secure flag enables creation of queues that can access protected content.

This matches the corresponding libdrm changes in commit fdf384d4b546
("amdgpu: add priority and secure flags for user queues").

Signed-off-by: Jesse.Zhang <Jesse.zhang at amd.com>
---
 lib/amdgpu/amd_ip_blocks.h  |  1 +
 lib/amdgpu/amd_user_queue.c | 15 +++++++++++----
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h index 231098eb8..7d48f9107 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -118,6 +118,7 @@ struct amdgpu_ring_context {
        uint32_t *pm4;          /* data of the packet */
        uint32_t pm4_size;      /* max allocated packet size */
        bool secure;            /* secure or not */
+       uint32_t priority;      /* user queue priority */

        uint64_t bo_mc;         /* GPU address of first buffer */
        uint64_t bo_mc2;        /* GPU address for p4 packet */
diff --git a/lib/amdgpu/amd_user_queue.c b/lib/amdgpu/amd_user_queue.c index 0cdd0c4f9..b396d0307 100644
--- a/lib/amdgpu/amd_user_queue.c
+++ b/lib/amdgpu/amd_user_queue.c
@@ -270,7 +270,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
                              unsigned int type)
 {
        int r;
-       uint64_t gtt_flags = 0;
+       uint64_t gtt_flags = 0, queue_flags = 0;
        struct drm_amdgpu_userq_mqd_gfx11 gfx_mqd;
        struct drm_amdgpu_userq_mqd_sdma_gfx11 sdma_mqd;
        struct drm_amdgpu_userq_mqd_compute_gfx11 compute_mqd; @@ -283,6 +283,13 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_

        if (ctxt->secure)
                gtt_flags |= AMDGPU_GEM_CREATE_ENCRYPTED;
+
+       if (ctxt->secure)
+               queue_flags |= AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE;
+
I think its better if you could add both the conditions under one if (ctxt->secure), with that in place its Reviewed-by: Sunil Khatri <sunil.khatri at amd.com>

+       if (ctxt->priority)
+               queue_flags |= ctxt->priority &
+AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK;
+
        r = amdgpu_query_uq_fw_area_info(device_handle, AMD_IP_GFX, 0, &ctxt->info);
        igt_assert_eq(r, 0);

@@ -404,7 +411,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
                                            ctxt->db_handle, DOORBELL_INDEX,
                                            ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
                                            ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
-                                           mqd, &ctxt->queue_id);
+                                           mqd, queue_flags, &ctxt->queue_id);
                igt_assert_eq(r, 0);
                break;

@@ -413,7 +420,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
                                            ctxt->db_handle, DOORBELL_INDEX,
                                            ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
                                            ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
-                                           mqd, &ctxt->queue_id);
+                                           mqd, queue_flags, &ctxt->queue_id);
                igt_assert_eq(r, 0);
                break;

@@ -422,7 +429,7 @@ void amdgpu_user_queue_create(amdgpu_device_handle device_handle, struct amdgpu_
                                            ctxt->db_handle, DOORBELL_INDEX,
                                            ctxt->queue.mc_addr, USERMODE_QUEUE_SIZE,
                                            ctxt->wptr.mc_addr, ctxt->rptr.mc_addr,
-                                           mqd, &ctxt->queue_id);
+                                           mqd, queue_flags, &ctxt->queue_id);
                igt_assert_eq(r, 0);
                break;

--
2.25.1