[PATCH i-g-t v2 1/2] drm-uapi/amdgpu: Add queue priority and secure flags definitions

[Kamil Konieczny]

Hi Jesse.zhang,
On 2025-04-17 at 16:52:46 +0800, Jesse.zhang at amd.com wrote:
> Add UAPI definitions for queue priority levels (NORMAL_LOW, LOW, etc.)
> and secure queue flag in amdgpu_drm.h. This matches the libdrm changes
> in commit fdf384d4b546 ("amdgpu: add priority and secure flags for user queues").

Please write from what tree comes this commit or
give lore.kernel.org link.

I tried to find out this on current drm-tip and failed,
am I missing something?

Regards,
Kamil

> 
> v2: In general, UAPI changes should be part of a different change and only uapi should be part of it (Sunil)
> 
> Signed-off-by: Jesse.Zhang <Jesse.zhang at amd.com>
> ---
>  include/drm-uapi/amdgpu_drm.h | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
> index 8191d0bd0..3f4813879 100644
> --- a/include/drm-uapi/amdgpu_drm.h
> +++ b/include/drm-uapi/amdgpu_drm.h
> @@ -329,6 +329,16 @@ union drm_amdgpu_ctx {
>  #define AMDGPU_USERQ_OP_CREATE	1
>  #define AMDGPU_USERQ_OP_FREE	2
>  
> +/* queue priority levels */
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK  0x3
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
> +/* for queues that need access to protected content */
> +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE  (1 << 2)
> +
>  /*
>   * This structure is a container to pass input configuration
>   * info for all supported userqueue related operations.
> @@ -355,7 +365,7 @@ struct drm_amdgpu_userq_in {
>  	 * and doorbell_offset in the doorbell bo.
>  	 */
>  	__u32   doorbell_offset;
> -	__u32 _pad;
> +	__u32 flags;
>  	/**
>  	 * @queue_va: Virtual address of the GPU memory which holds the queue
>  	 * object. The queue holds the workload packets.
> -- 
> 2.25.1
>