[PATCH v3 1/2] uapi/xe: Sync latest uAPI KMD headers
Cavitt, Jonathan
jonathan.cavitt at intel.com
Thu Apr 24 22:32:01 UTC 2025
-----Original Message-----
> From: igt-dev <igt-dev-bounces at lists.freedesktop.org> On Behalf Of Matthew Brost
> Sent: Thursday, April 24, 2025 1:44 PM
> To: igt-dev at lists.freedesktop.org
> Cc: Dugast, Francois <francois.dugast at intel.com>
> Subject: [PATCH v3 1/2] uapi/xe: Sync latest uAPI KMD headers
>
> Pull in latest uAPI KMD headers to enable testing of new features.
>
> Signed-off-by: Matthew Brost <matthew.brost at intel.com>
LGTM, though I am a bit surprised that cpu_addr_mirror_offset is
a signed integer and not a uint.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
-Jonathan Cavitt
> ---
> include/drm-uapi/xe_drm.h | 49 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 154f947ef0..c90fab1b00 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -393,6 +393,10 @@ struct drm_xe_query_mem_regions {
> *
> * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
> * has usable VRAM
> + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device
> + * has low latency hint support
> + * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
> + * device has CPU address mirroring support
> * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
> * required by this device, typically SZ_4K or SZ_64K
> * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
> @@ -409,6 +413,8 @@ struct drm_xe_query_config {
> #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
> #define DRM_XE_QUERY_CONFIG_FLAGS 1
> #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
> + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY (1 << 1)
> + #define DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR (1 << 2)
> #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
> #define DRM_XE_QUERY_CONFIG_VA_BITS 3
> #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
> @@ -911,7 +917,11 @@ struct drm_xe_gem_mmap_offset {
> * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
> *
> * The @flags can be:
> - * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE
> + * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
> + * space of the VM to scratch page. A vm_bind would overwrite the scratch
> + * page mapping. This flag is mutually exclusive with the
> + * %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and
> + * xe3 platform.
> * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
> * exec submissions to its exec_queues that don't have an upper time
> * limit on the job execution time. But exec submissions to these
> @@ -987,6 +997,12 @@ struct drm_xe_vm_destroy {
> * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP,
> * reject the binding if the encryption key is no longer valid. This
> * flag has no effect on BOs that are not marked as using PXP.
> + * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is
> + * set, no mappings are created rather the range is reserved for CPU address
> + * mirroring which will be populated on GPU page faults or prefetches. Only
> + * valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
> + * mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
> + * handle MBZ, and the BO offset MBZ.
> */
> struct drm_xe_vm_bind_op {
> /** @extensions: Pointer to the first extension struct, if any */
> @@ -1039,7 +1055,9 @@ struct drm_xe_vm_bind_op {
> * on the @pat_index. For such mappings there is no actual memory being
> * mapped (the address in the PTE is invalid), so the various PAT memory
> * attributes likely do not apply. Simply leaving as zero is one
> - * option (still a valid pat_index).
> + * option (still a valid pat_index). Same applies to
> + * DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR bindings as for such mapping
> + * there is no actual memory being mapped.
> */
> __u16 pat_index;
>
> @@ -1055,6 +1073,14 @@ struct drm_xe_vm_bind_op {
>
> /** @userptr: user pointer to bind on */
> __u64 userptr;
> +
> + /**
> + * @cpu_addr_mirror_offset: Offset from GPU @addr to create
> + * CPU address mirror mappings. MBZ with current level of
> + * support (e.g. 1 to 1 mapping between GPU and CPU mappings
> + * only supported).
> + */
> + __s64 cpu_addr_mirror_offset;
> };
>
> /**
> @@ -1078,6 +1104,7 @@ struct drm_xe_vm_bind_op {
> #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2)
> #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3)
> #define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4)
> +#define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5)
> /** @flags: Bind flags */
> __u32 flags;
>
> @@ -1205,6 +1232,21 @@ struct drm_xe_vm_bind {
> * };
> * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
> *
> + * Allow users to provide a hint to kernel for cases demanding low latency
> + * profile. Please note it will have impact on power consumption. User can
> + * indicate low latency hint with flag while creating exec queue as
> + * mentioned below,
> + *
> + * struct drm_xe_exec_queue_create exec_queue_create = {
> + * .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT,
> + * .extensions = 0,
> + * .vm_id = vm,
> + * .num_bb_per_exec = 1,
> + * .num_eng_per_bb = 1,
> + * .instances = to_user_pointer(&instance),
> + * };
> + * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
> + *
> */
> struct drm_xe_exec_queue_create {
> #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
> @@ -1223,7 +1265,8 @@ struct drm_xe_exec_queue_create {
> /** @vm_id: VM to use for this exec queue */
> __u32 vm_id;
>
> - /** @flags: MBZ */
> +#define DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT (1 << 0)
> + /** @flags: flags to use for this exec queue */
> __u32 flags;
>
> /** @exec_queue_id: Returned exec queue ID */
> --
> 2.34.1
>
>
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