[PATCH] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL
Lucas De Marchi
lucas.demarchi at intel.com
Fri Feb 7 21:04:44 UTC 2025
On Thu, Feb 06, 2025 at 11:44:47AM -0800, Matt Roper wrote:
>On Thu, Feb 06, 2025 at 02:35:31PM -0500, Rodrigo Vivi wrote:
>> On Thu, Feb 06, 2025 at 11:26:05AM -0800, Matt Atwood wrote:
>> > On Thu, Feb 06, 2025 at 10:01:13AM -0800, Matt Roper wrote:
>> > > On Thu, Feb 06, 2025 at 09:06:32AM -0800, Matt Atwood wrote:
>> > > > On Wed, Feb 05, 2025 at 03:30:55PM -0800, Matt Roper wrote:
>> > > > > On Tue, Feb 04, 2025 at 09:53:02AM -0800, Matt Atwood wrote:
>> > > > > > There have been several changes to pciids upstream that need to be
>> > > > > > sync'd into igt.
>> > > > > >
>> > > > > > Sync with the following kernel commits:
>> > > > > > f9a15b968dce ("drm/intel/pciids: Refactor DG2 PCI IDs into segment
>> > > > > > ranges")
>> > > > > > e35ecd95ecf2 ("drm/i915/display: Add MTL subplatforms definition")
>> > > > > > fa8ffaae1b15 ("drm/xe/bmg: Add new PCI IDs")
>> > > > > > 16016ade13f6 ("drm/xe/ptl: Update the PTL pci id table")
>> > > > >
>> > > > > The updates below look correct (they match the kernel header), but the
>> > > > > commit message here is confusing. IGT updates to this file generally
>> > > > > specify which actual kernel commit you're synchronizing against; none of
>> > > > > the four listed above match the content you've copied here because there
>> > > > > are additional changes not present in those.
>> > > > Because there are now several out of sync next branches, saying as
>> > > > of this commit idea was not working. Hence this approach.
>> > >
>> > > You should generally be syncing with drm-next after things land there.
>> > > So which drm-next commit are you syncing with for this commit?
>> > They hadnt been in a drm-next commit yet. At the time it was just after
>> > a next cut, at this point we can probably just wait for them to land.
>>
>> I agree with Atwood here. We had changes coming from drm-intel-next
>> and changes coming to drm-xe-next. In the kernel history the changes
>> coming from drm-xe-next are on top of the drm-intel-next ones. But
>> they landed first here in the IGT.
>>
>> Now it is in a situation that individual patches from drm-intel-next
>> would conflict here badly. The safest thing is to keep it simple and
>> use a single patch like this.
>>
>> This is the final copy of the file directly with the proper mention
>> to the commit ids. I really believe we should just go ahead and push
>> this to finalize the alignment before something else gets in the way.
>
>But in that case we should be explain what we're actually doing in the
>commit message. I.e., we're *not* synchronizing IGT with a kernel
>commit like we usually do. Instead we're manually rolling up individual
>changes from various kernel branches before they propagate into
>drm-next.
>
>As I said before, the actual patch is fine; we just need to fix the
>commit message to more accurately reflect what's happening, especially
>since it's not how we usually handle things in IGT.
I think being explicit of what was done would be: 1) show what was the
drm-tip used; 2) mention the changes that are contained.
Example:
lib/pciids: sync with kernel
Synch PCI IDs with kernel, up to drm-tip commit
a293777d70b3 ("drm-tip: 2025y-02m-07d-16h-56m-38s UTC integration manifest"),
which contains the following additional commits since last synchronized:
16016ade13f69 drm/xe/ptl: Update the PTL pci id table
fa8ffaae1b152 drm/xe/bmg: Add new PCI IDs
e35ecd95ecf28 drm/i915/display: Add MTL subplatforms definition
6a04bb5a20460 drm/xe: remove unused xe_pciids.h harder, add missing PCI ID
b99dcb91ef551 drm/intel/pciids: Refactor DG2 PCI IDs into segment ranges
^ this was obtained with
$ git log --format=short --oneline --no-merges \
3c1d5ced18db..HEAD include/drm/intel/pciids.h
If instead we want to show the commits from -next branches, we could do:
$ git log --format="%h %s" --merges 3c1d5ced18db..HEAD -- include/drm/intel/pciids.h \
| while read -r h x; do echo "$h $x"; git log --format=" %h %s" -1 $h^2; done
f28030b19c846 Merge remote-tracking branch 'kernel/drm-xe-next' into drm-tip
5b380838930f1 drm/xe: Add stats for vma page faults
ea9f8f2b21795 Merge drm/drm-next into drm-intel-next
2014c95afecee Linux 6.14-rc1
220ed690436e9 Merge drm/drm-next into drm-xe-next
1c470f4f61f3d Merge tag 'amd-drm-fixes-6.14-2025-01-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
0dc853865ab52 Merge tag 'drm-xe-next-2025-01-10' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next
6a04bb5a20460 drm/xe: remove unused xe_pciids.h harder, add missing PCI ID
28eb75e178d38 Merge tag 'drm-next-2024-11-21' of https://gitlab.freedesktop.org/drm/kernel
a163b89507786 Merge tag 'drm-xe-next-fixes-2024-11-15' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next
Lucas De Marchi
>
>
>Matt
>
>>
>> >
>> > MattA
>> > >
>> > >
>> > > Matt
>> > >
>> > > >
>> > > > MattA
>> > > > >
>> > > > >
>> > > > > Matt
>> > > > >
>> > > > > >
>> > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
>> > > > > > ---
>> > > > > > lib/pciids.h | 62 +++++++++++++++++++++++++++++++++++++++-------------
>> > > > > > 1 file changed, 47 insertions(+), 15 deletions(-)
>> > > > > >
>> > > > > > diff --git a/lib/pciids.h b/lib/pciids.h
>> > > > > > index 23f349f65..4736ea525 100644
>> > > > > > --- a/lib/pciids.h
>> > > > > > +++ b/lib/pciids.h
>> > > > > > @@ -717,37 +717,66 @@
>> > > > > > MACRO__(0xA7AB, ## __VA_ARGS__)
>> > > > > >
>> > > > > > /* DG2 */
>> > > > > > -#define INTEL_DG2_G10_IDS(MACRO__, ...) \
>> > > > > > - MACRO__(0x5690, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x5691, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x5692, ## __VA_ARGS__), \
>> > > > > > +#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
>> > > > > > MACRO__(0x56A0, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56A1, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x56A2, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x56A2, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
>> > > > > > MACRO__(0x56BE, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56BF, ## __VA_ARGS__)
>> > > > > >
>> > > > > > -#define INTEL_DG2_G11_IDS(MACRO__, ...) \
>> > > > > > - MACRO__(0x5693, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x5694, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x5695, ## __VA_ARGS__), \
>> > > > > > +#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
>> > > > > > + MACRO__(0x5690, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x5691, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x5692, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G10_IDS(MACRO__, ...) \
>> > > > > > + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
>> > > > > > MACRO__(0x56A5, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56A6, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56B0, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x56B1, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x56B1, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
>> > > > > > MACRO__(0x56BA, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56BB, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56BC, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56BD, ## __VA_ARGS__)
>> > > > > >
>> > > > > > -#define INTEL_DG2_G12_IDS(MACRO__, ...) \
>> > > > > > - MACRO__(0x5696, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x5697, ## __VA_ARGS__), \
>> > > > > > +#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
>> > > > > > + MACRO__(0x5693, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x5694, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x5695, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G11_IDS(MACRO__, ...) \
>> > > > > > + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
>> > > > > > MACRO__(0x56A3, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56A4, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56B2, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x56B3, ## __VA_ARGS__)
>> > > > > >
>> > > > > > +#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
>> > > > > > + MACRO__(0x5696, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x5697, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
>> > > > > > + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_DG2_D_IDS(MACRO__, ...) \
>> > > > > > + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > #define INTEL_DG2_IDS(MACRO__, ...) \
>> > > > > > INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > @@ -782,9 +811,12 @@
>> > > > > > INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
>> > > > > >
>> > > > > > /* MTL */
>> > > > > > -#define INTEL_MTL_IDS(MACRO__, ...) \
>> > > > > > +#define INTEL_MTL_U_IDS(MACRO__, ...) \
>> > > > > > MACRO__(0x7D40, ## __VA_ARGS__), \
>> > > > > > - MACRO__(0x7D45, ## __VA_ARGS__), \
>> > > > > > + MACRO__(0x7D45, ## __VA_ARGS__)
>> > > > > > +
>> > > > > > +#define INTEL_MTL_IDS(MACRO__, ...) \
>> > > > > > + INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x7D55, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x7D60, ## __VA_ARGS__), \
>> > > > > > MACRO__(0x7DD5, ## __VA_ARGS__)
>> > > > > > --
>> > > > > > 2.45.0
>> > > > > >
>> > > > >
>> > > > > --
>> > > > > Matt Roper
>> > > > > Graphics Software Engineer
>> > > > > Linux GPU Platform Enablement
>> > > > > Intel Corporation
>> > >
>> > > --
>> > > Matt Roper
>> > > Graphics Software Engineer
>> > > Linux GPU Platform Enablement
>> > > Intel Corporation
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
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