[PATCH i-g-t] lib/xe: Fix allocation for vram_size and visible_vram_size based on max_gt

Gustavo Sousa gustavo.sousa at intel.com
Thu Jul 10 22:12:27 UTC 2025


The current allocation for vram_size and visible_vram_size has two
issues:

* The expression (max_gt = ffsll(xe_dev->gt_mask) - 1) gives us the
  zero-based index of the first bit set in the mask, which does not give
  us the maximum GT ID, but the minimum.

* Since max_gt is zero-based, even if its value was right, we would
  still be allocating not enough entries for the array.

Fix that by calculating max_gt in the same way that xe_dev_max_gt() does
and using (max_gt + 1) as argument to calloc().

Cc: Matt Roper <matthew.d.roper at intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
Fixes: 3a39a6e51b18 ("lib/xe: Populate vram_size[] and visible_vram_size[] by GT ID")
Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
---
 lib/xe/xe_query.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c
index 3d628cb3fe59ddc390684941452ca04fd735b212..c0dba018244e8a47c8f1b305cf43ec3d4ffdc575 100644
--- a/lib/xe/xe_query.c
+++ b/lib/xe/xe_query.c
@@ -361,9 +361,9 @@ struct xe_device *xe_device_get(int fd)
 	 * vram_size[] and visible_vram_size[] are indexed by uapi ID; ensure
 	 * the allocation is large enough to hold the highest GT ID
 	 */
-	max_gt = ffsll(xe_dev->gt_mask) - 1;
-	xe_dev->vram_size = calloc(max_gt, sizeof(*xe_dev->vram_size));
-	xe_dev->visible_vram_size = calloc(max_gt, sizeof(*xe_dev->visible_vram_size));
+	max_gt = igt_fls(xe_dev->gt_mask) - 1;
+	xe_dev->vram_size = calloc(max_gt + 1, sizeof(*xe_dev->vram_size));
+	xe_dev->visible_vram_size = calloc(max_gt + 1, sizeof(*xe_dev->visible_vram_size));
 
 	for (int idx = 0; idx < xe_dev->gt_list->num_gt; idx++) {
 		struct drm_xe_gt *gt = &xe_dev->gt_list->gt_list[idx];

---
base-commit: eacde5c2acc37c1570e27b68b8b6c39d8b61fb32
change-id: 20250710-fix-allocation-of-vram_size-and-visible_vram_size-f194f0e55610

Best regards,
-- 
Gustavo Sousa <gustavo.sousa at intel.com>



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