[PATCH i-g-t 1/3] lib/amdgpu: add timeout support for user queue submissions

[vitaly prosyak]

The change looks good to me

Reviewed-by Vitaly Prosyak <vitaly.prosyak at amd.com>

On 2025-05-08 22:33, vitaly prosyak wrote:
> The change looks good to me
>
> Reviewed-by Vitaly Prosyak <vitaly.prosyak at amd.com>
>
> On 2025-05-08 02:07, Jesse.Zhang wrote:
>> This patch adds timeout control for user queue operations in IGT's AMDGPU
>> tests by:
>>
>> 1. Adding a time_out field to struct amdgpu_ring_context to store per-ring
>>    timeout values
>> 2. Modifying amdgpu_user_queue_submit() to use the specified timeout or
>>    default to INT64_MAX (infinite wait) if not set
>> 3. Passing the timeout value to amdgpu_cs_syncobj_wait()
>>
>> The changes allow tests to specify timeout values for user queue operations
>> rather than always using an infinite wait. This provides better control
>> over test execution and helps prevent hangs during test development and
>> debugging.
>>
>> Cc: Prosyak, Vitaly <Vitaly.Prosyak at amd.com>
>> Cc: Sunil Khatri <sunil.khatri at amd.com>
>> Cc: Christian Koenig <christian.koenig at amd.com>
>> Cc: Alexander Deucher <alexander.deucher at amd.com>
>>
>> Signed-off-by: Jesse Zhang <jesse.zhang at amd.com>
>> ---
>>  lib/amdgpu/amd_command_submission.c | 3 +++
>>  lib/amdgpu/amd_ip_blocks.h          | 1 +
>>  lib/amdgpu/amd_userq.c              | 4 ++--
>>  3 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/lib/amdgpu/amd_command_submission.c b/lib/amdgpu/amd_command_submission.c
>> index 80d03a498..fcc356f8f 100644
>> --- a/lib/amdgpu/amd_command_submission.c
>> +++ b/lib/amdgpu/amd_command_submission.c
>> @@ -153,6 +153,7 @@ void amdgpu_command_submission_write_linear_helper(amdgpu_device_handle device,
>>  	ring_context->pm4_size = pm4_dw;
>>  	ring_context->res_cnt = 1;
>>  	ring_context->user_queue = user_queue;
>> +	ring_context->time_out = 0;
>>  	igt_assert(ring_context->pm4);
>>  
>>  	r = amdgpu_query_hw_ip_info(device, ip_block->type, 0, &ring_context->hw_ip_info);
>> @@ -280,6 +281,7 @@ void amdgpu_command_submission_const_fill_helper(amdgpu_device_handle device,
>>  	ring_context->pm4_size = pm4_dw;
>>  	ring_context->res_cnt = 1;
>>  	ring_context->user_queue = user_queue;
>> +	ring_context->time_out = 0;
>>  	igt_assert(ring_context->pm4);
>>  	r = amdgpu_query_hw_ip_info(device, ip_block->type, 0, &ring_context->hw_ip_info);
>>  	igt_assert_eq(r, 0);
>> @@ -374,6 +376,7 @@ void amdgpu_command_submission_copy_linear_helper(amdgpu_device_handle device,
>>  	ring_context->pm4_size = pm4_dw;
>>  	ring_context->res_cnt = 2;
>>  	ring_context->user_queue = user_queue;
>> +	ring_context->time_out = 0;
>>  	igt_assert(ring_context->pm4);
>>  	r = amdgpu_query_hw_ip_info(device, ip_block->type, 0, &ring_context->hw_ip_info);
>>  	igt_assert_eq(r, 0);
>> diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
>> index 3c2ecd1ba..a6c35c171 100644
>> --- a/lib/amdgpu/amd_ip_blocks.h
>> +++ b/lib/amdgpu/amd_ip_blocks.h
>> @@ -175,6 +175,7 @@ struct amdgpu_ring_context {
>>  	uint32_t timeline_syncobj_handle;
>>  	uint64_t point;
>>  	bool user_queue;
>> +	uint64_t time_out;
>>  
>>  	struct drm_amdgpu_info_uq_fw_areas info;
>>  };
>> diff --git a/lib/amdgpu/amd_userq.c b/lib/amdgpu/amd_userq.c
>> index 50d058609..f8e1a4b45 100644
>> --- a/lib/amdgpu/amd_userq.c
>> +++ b/lib/amdgpu/amd_userq.c
>> @@ -133,7 +133,7 @@ void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_co
>>  	uint32_t control = ring_context->pm4_dw;
>>  	uint32_t syncarray[1];
>>  	struct drm_amdgpu_userq_signal signal_data;
>> -
>> +	uint64_t timeout = ring_context->time_out ? ring_context->time_out : INT64_MAX;
>>  
>>  	amdgpu_pkt_begin();
>>  	/* Prepare the Indirect IB to submit the IB to user queue */
>> @@ -179,7 +179,7 @@ void amdgpu_user_queue_submit(amdgpu_device_handle device, struct amdgpu_ring_co
>>  	r = amdgpu_userq_signal(device, &signal_data);
>>  	igt_assert_eq(r, 0);
>>  
>> -	r = amdgpu_cs_syncobj_wait(device, &ring_context->timeline_syncobj_handle, 1, INT64_MAX,
>> +	r = amdgpu_cs_syncobj_wait(device, &ring_context->timeline_syncobj_handle, 1, timeout,
>>  				   DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL, NULL);
>>  	igt_assert_eq(r, 0);
>>  }