[PATCH 1/3] tests/intel/xe_exec_system_allocator: Test to validate basic SVM functionality

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces at lists.freedesktop.org> On Behalf Of sai.gowtham.ch at intel.com
Sent: Tuesday, May 13, 2025 10:07 AM
To: igt-dev at lists.freedesktop.org; Ch, Sai Gowtham <sai.gowtham.ch at intel.com>; Ghimiray, Himal Prasad <himal.prasad.ghimiray at intel.com>; Brost, Matthew <matthew.brost at intel.com>
Subject: [PATCH 1/3] tests/intel/xe_exec_system_allocator: Test to validate basic SVM functionality
> 
> From: Sai Gowtham Ch <sai.gowtham.ch at intel.com>
> 
> Basic test validates basic SVM functionlity.

s/functionlity/functionality

There's also a non-blocking comment below, but otherwise:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>

> 
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> Cc: Matthew Brost <matthew.brost at intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch at intel.com>
> ---
>  tests/intel/xe_exec_system_allocator.c | 64 ++++++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_system_allocator.c b/tests/intel/xe_exec_system_allocator.c
> index 06daac8c2..ba11ed834 100644
> --- a/tests/intel/xe_exec_system_allocator.c
> +++ b/tests/intel/xe_exec_system_allocator.c
> @@ -32,6 +32,8 @@
>  struct batch_data {
>  	uint32_t batch[16];
>  	uint64_t pad;
> +	uint64_t vm_sync;
> +	uint64_t exec_sync;
>  	uint32_t data;
>  	uint32_t expected_data;
>  };
> @@ -405,6 +407,63 @@ static void __aligned_partial_free(struct aligned_alloc_type  *aligned_alloc_typ
>  		       aligned_alloc_type->__size - aligned_alloc_type->size - begin_size);
>  }
>  
> +/**
> + * SUBTEST: basic-svm
> + * Description: Test validates basic svm.
> + * Test category: functionality test
> + */
> +static void test_basic(int fd, struct drm_xe_engine_class_instance *eci,
> +		       size_t bo_size, int num_dwords)
> +{
> +	uint64_t addr;
> +	struct drm_xe_sync sync[1] = {
> +		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE, .flags = DRM_XE_SYNC_FLAG_SIGNAL,
> +		  .timeline_value = USER_FENCE_VALUE },
> +	};
> +	struct drm_xe_exec exec = {
> +		.num_batch_buffer = 1,
> +		.num_syncs = 1,
> +		.syncs = to_user_pointer(sync),
> +	};
> +	struct batch_data *data;
> +	uint32_t exec_queues, vm;
> +	size_t aligned_size = bo_size ?: xe_get_default_alignment(fd);
> +
> +	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
> +	data = aligned_alloc(aligned_size, bo_size);
> +	igt_assert(data != NULL);
> +	memset(data, 0, bo_size);
> +
> +	exec_queues = xe_exec_queue_create(fd, vm, eci, 0);
> +	sync[0].addr = to_user_pointer(&data[0].vm_sync);
> +	bind_system_allocator(sync, 1);
> +	xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
> +	data[0].vm_sync = 0;
> +
> +	addr = to_user_pointer(data);
> +	for (int i = 0; i <= num_dwords; i++) {
> +		uint64_t batch_offset = (char *)&data[i].batch - (char *)data;
> +		uint64_t batch_addr = addr + batch_offset;
> +		uint64_t sdi_offset = (char *)&(data[i].data) - (char *)data;
> +		uint64_t sdi_addr = addr + sdi_offset;
> +		int b = 0;
> +
> +		write_dword(data[i].batch, sdi_addr, WRITE_VALUE(&data[i], i), &b);
> +		igt_assert(b <= ARRAY_SIZE(data[i].batch));
> +
> +		exec.exec_queue_id = exec_queues;
> +		exec.address = batch_addr;
> +		sync[0].addr = addr + (char *)&data[i].exec_sync - (char *)data;
> +		xe_exec(fd, &exec);
> +		xe_wait_ufence(fd, &data[i].exec_sync, USER_FENCE_VALUE, exec_queues, NSEC_PER_SEC);
> +		data[i].exec_sync = 0;
> +		igt_assert_eq(data[i].data, READ_VALUE(&data[i]));
> +	}
> +	unbind_system_allocator();
> +	free(data);
> +	xe_exec_queue_destroy(fd, exec_queues);
> +	xe_vm_destroy(fd, vm);
> +}
>  /**
>   * SUBTEST: unaligned-alloc
>   * Description: allocate unaligned sizes of memory
> @@ -1597,6 +1656,7 @@ struct section {
>  
>  igt_main
>  {
> +	struct drm_xe_engine *engine;
>  	struct drm_xe_engine_class_instance *hwe;
>  	const struct section sections[] = {
>  		{ "malloc", 0 },
> @@ -1695,11 +1755,15 @@ igt_main
>  		fd = drm_open_driver(DRIVER_XE);
>  		igt_require(!xe_supports_faults(fd));
>  
> +		engine = xe_engine(fd, 1);

Non-blocking:
If you just need to get "any" engine, then you might be able to "hijack" the
pre-existing drm_xe_engine_class_instance *hwe above for that purpose.
Though, you'd need to declare it using a fixture beforehand.  Something like:

"""
igt_fixture {
	/* Get first engine */
	xe_for_each_engine(fd, hwe)
		break;
}
"""

We could also still use xe_engine, but it doesn't look quite as elegant:

"""
igt_fixture {
	/* Get first engine */
	hwe = &xe_engine(fd, 1)->instance;
}
"""

Then, the below subtest would look like:

"""
igt_subtest("basic_svm")
	test_basic(fd, hwe, SZ_64K, 1);
"""

Note that we'd also need to place the subtests in the next two patches
after this fixture and before the subtest below it (once-%s), lest we need to
repeat this fixture process again for those new subtests.

It's not particularly important we use the hwe in this way, so I won't block on it.
But it would be nice to avoid any additional variables where we can.
-Jonathan Cavitt

>  		xe = xe_device_get(fd);
>  		va_bits = xe->va_bits;
>  		open_sync_file();
>  	}
>  
> +	igt_subtest("basic-svm")
> +		test_basic(fd, &engine->instance, SZ_64K, 1);
> +
>  	for (const struct section *s = sections; s->name; s++) {
>  		igt_subtest_f("once-%s", s->name)
>  			xe_for_each_engine(fd, hwe)
> -- 
> 2.34.1
> 
>