[PATCH 3/3] tests/intel/xe_exec_system_allocator: Rebind the prefetch ranges

[Cavitt, Jonathan]

-----Original Message-----
From: Ch, Sai Gowtham <sai.gowtham.ch at intel.com> 
Sent: Wednesday, May 14, 2025 1:58 PM
To: igt-dev at lists.freedesktop.org; Ch, Sai Gowtham <sai.gowtham.ch at intel.com>; Ghimiray, Himal Prasad <himal.prasad.ghimiray at intel.com>; Brost, Matthew <matthew.brost at intel.com>; Cavitt, Jonathan <jonathan.cavitt at intel.com>
Subject: [PATCH 3/3] tests/intel/xe_exec_system_allocator: Rebind the prefetch ranges
> 
> From: Sai Gowtham Ch <sai.gowtham.ch at intel.com>
> 
> Test rebinds the prefetch ranges to check the ideal behaviour of prefetch mechanism,
> expecting address ranges in the corresponding mem regions has to be created again and
> use those address ranges to submit workloads.
> 
> v2: Enhance VRAM/SMEM/BIND flags in the selection loop of this test. (Jonathan Cavitt)
> 
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> Cc: Matthew Brost <matthew.brost at intel.com>
> Cc: Jonathan Cavitt <jonathan.cavitt at intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch at intel.com>

No additional notes:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
-Jonathan Cavitt

> ---
>  tests/intel/xe_exec_system_allocator.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/tests/intel/xe_exec_system_allocator.c b/tests/intel/xe_exec_system_allocator.c
> index d4f2e8d98..227c60d76 100644
> --- a/tests/intel/xe_exec_system_allocator.c
> +++ b/tests/intel/xe_exec_system_allocator.c
> @@ -141,6 +141,7 @@ static void signal_pdata(struct process_data *pdata)
>  #define CPU_FAULT_PROCESS	(0x1 << 3)
>  #define CPU_FAULT_SAME_PAGE	(0x1 << 4)
>  #define VRAM			(0x1 << 5)
> +#define BIND			(0x1 << 6)
>  
>  static void process_check(void *ptr, uint64_t alloc_size, uint64_t stride,
>  			  unsigned int flags)
> @@ -484,6 +485,12 @@ static void test_basic(int fd, struct drm_xe_engine_class_instance *eci,
>   * @vram-SZ_4K: with size of SZ_4K on vram region
>   * @vram-SZ_64K: with size of SZ_64K on vram region
>   * @vram-SZ_2M: with size of SZ_2M on vram region
> + * @bind-smem-SZ_4K: with size of SZ_4K on vram and rebinding of smem region
> + * @bind-smem-SZ_64K: with size of SZ_64K on vram and rebinding of smem region
> + * @bind-smem-SZ_2M: with size of SZ_2M on vram and rebinding of smem region
> + * @bind-vram-SZ_4K: with size of SZ_4K on smem and rebinding of vram region
> + * @bind-vram-SZ_64K: with size of SZ_64K on smem and rebinding of vram region
> + * @bind-vram-SZ_2M: with size of SZ_2M on smem and rebinding of vram region
>   */
>  #define MAX_BATCH_DWORDS 16
>  static void prefetch(int fd, struct drm_xe_engine_class_instance *eci,
> @@ -538,6 +545,13 @@ static void prefetch(int fd, struct drm_xe_engine_class_instance *eci,
>  	xe_vm_prefetch_async(fd, vm, 0, 0, addr, bo_size, sync, 1, flags & VRAM ? 1 : 0);
>  	xe_wait_ufence(fd, exec_ufence, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
>  	exec.exec_queue_id = exec_queues;
> +	if (flags & BIND) {
> +		exec_ufence[0] = 0;
> +		sync[0].addr = to_user_pointer(exec_ufence);
> +		xe_vm_prefetch_async(fd, vm, 0, 0, addr, bo_size, sync, 1, flags & VRAM ? 0 : 1);
> +		xe_wait_ufence(fd, exec_ufence, USER_FENCE_VALUE, 0, NSEC_PER_SEC);
> +		exec_ufence[0] = 0;
> +	}
>  
>  	for (int i = 0; i < num_dwords; i++) {
>  		result_ptr = (uint32_t *)((uint8_t *)data + i * slice_size + 0x100);
> @@ -1765,6 +1779,13 @@ igt_main
>  		{ "vram-SZ_4K", VRAM, SZ_4K},
>  		{ "vram-SZ_64K", VRAM, SZ_64K},
>  		{ "vram-SZ_2M", VRAM, SZ_2M},
> +		{ "bind-smem-SZ_4K", VRAM | BIND, SZ_4K},
> +		{ "bind-smem-SZ_64K", VRAM | BIND, SZ_64K},
> +		{ "bind-smem-SZ_2M", VRAM | BIND, SZ_2M},
> +		{ "bind-vram-SZ_4K", BIND, SZ_4K},
> +		{ "bind-vram-SZ_64K", BIND, SZ_64K},
> +		{ "bind-vram-SZ_2M", BIND, SZ_2M},
> +		{ NULL },
>  		{},
>  	}, *m;
>  
> -- 
> 2.34.1
> 
>