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<div class="moz-cite-prefix">On 3/26/2024 11:09, Piórkowski, Piotr
wrote:<br>
</div>
<blockquote type="cite">
<pre class="moz-quote-pre" wrap="">From: Piotr Piórkowski <a class="moz-txt-link-rfc2396E" href="mailto:piotr.piorkowski@intel.com"><piotr.piorkowski@intel.com></a>
Previously, we limited BAR0 mapping to register space only because of
the potential conflict with wc mapping for the GTT region.
For gen12+ platforms, the size of BAR0 varies due to the different amount
of tile.
And as for gen11+ platforms, we can already map the whole BAR0 as uc,
so let's map the whole BAR0, without artificial limitations.
Signed-off-by: Piotr Piórkowski <a class="moz-txt-link-rfc2396E" href="mailto:piotr.piorkowski@intel.com"><piotr.piorkowski@intel.com></a>
---
lib/intel_mmio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
index 4b6820787..31975727e 100644
--- a/lib/intel_mmio.c
+++ b/lib/intel_mmio.c
@@ -154,7 +154,7 @@ intel_mmio_use_pci_bar(struct intel_mmio_data *mmio_data, struct pci_device *pci
gen = intel_gen(devid);
if (gen >= 12)
- mmio_size = 8 * 1024 * 1024;
+ mmio_size = pci_dev->regions[mmio_bar].size;
else if (gen >= 5)
mmio_size = 2 * 1024 * 1024;
else</pre>
</blockquote>
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<p><span lang="en-US">Reviewed-by: </span><span lang="pl">L</span><span lang="en-US">ukasz </span><span lang="pl">L</span><span lang="en-US">aguna <</span><a href="mailto:lukasz.laguna@intel.com"><span lang="en-US">lukasz.laguna@intel.com</span></a><span lang="en-US">></span><span style="white-space: pre-wrap">
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