[Bug 86242] New: [BDW Bisected] Unigine-valley_1_0 performance reduced ~10%

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=86242

            Bug ID: 86242
           Summary: [BDW Bisected] Unigine-valley_1_0 performance reduced
                    ~10%
           Product: Mesa
           Version: unspecified
          Hardware: Other
                OS: All
            Status: NEW
          Severity: normal
          Priority: medium
         Component: Drivers/DRI/i965
          Assignee: idr at freedesktop.org
          Reporter: wendy.wang at intel.com
        QA Contact: intel-3d-bugs at lists.freedesktop.org

Created attachment 109389
  --> https://bugs.freedesktop.org/attachment.cgi?id=109389&action=edit
Xor.0.log

Environment:
-----------------------------------
Platform:BDW GT2 E2
 Libdrm:       
(master)libdrm-2.4.58-4-g00847fa48b83a85b0cb882594a12ed1511f780db
 Mesa:        (master)f7819650979d1fa5339af3eacfa1af1090bf53e8
 Xserver:       
(master)xorg-server-1.16.99.901-3-g63bb5c5ef16edf652179770294dcca4fc07dc992
 Xf86_video_intel:       
(master)2.99.916-127-gcc3b8a542ecb1ba873efefaeab630fa8f69b5b96
 Cairo:        (master)adbeb3d53c6c6e8ddcc63988200da4c5c9627717
 Libva:        (master)ccd93de5a707e92a629cccd595757c8d436fa3cc
 Libva_intel_driver:        (master)24cba20a119c96556ae4dc9a90043896ea70e567
 Kernel:   (drm-intel-nightly)782bafb46cc12737b16e5007583bd7b534c6202a

Bug detailed description:
---------------------------------------------
unigine-valley_1_0 performance reduced ~10% on BDW

It's Mesa regression,bisect result shows below one is the first bad commit:

commit 7423cc891b4d6fcc63bfeb79cc1d711ce81122bd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Oct 22 08:58:58 2014 -0700

    i965: Implement the PMA stall fix.

    Certain non-promoted depth cases typically incur stalls.  In very
    specific cases, we can enable a workaround which improves performance.

    Improves performance in GLBenchmark 2.7 TRex by 1.17762% +/- 0.448765%
    (n=75) at 1280x720 on Broadwell GT3.

    Haswell has this feature as well, but we can't currently write registers
    from userspace batches (and we'd incur additional software batch
    scanning overhead as well), so we haven't enabled it.  Broadwell allows
    us to write CACHE_MODE_1.  Backporters beware: the formula and flushing
    incantation differs between Haswell and Broadwell.

    v2: Move pma_stall_bits from brw->state to brw itself (requested by
        Kristian Høgsberg).

    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>



Reproduce steps:
---------------------------------------------
1.            xinit&
2.            ./ unigine-valley_1_0

Xor.0.log attached.

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