[Bug 84826] [BSW Bisected]Piglit shaders_glsl-routing fails

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=84826

lu hua <huax.lu at intel.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[BSW Regression]Piglit      |[BSW Bisected]Piglit
                   |shaders_glsl-routing fails  |shaders_glsl-routing fails

--- Comment #5 from lu hua <huax.lu at intel.com> ---
Bisect shows: 7210583eb84a5d49803dbe37b0960373b4224d10 is the first bad commit.
commit 7210583eb84a5d49803dbe37b0960373b4224d10
Author:     Jason Ekstrand <jason.ekstrand at intel.com>
AuthorDate: Mon Aug 18 14:27:55 2014 -0700
Commit:     Jason Ekstrand <jason.ekstrand at intel.com>
CommitDate: Tue Sep 30 10:29:14 2014 -0700

    i965/fs_reg: Allocate double the number of vgrfs in SIMD16 mode

    This is actually the squash of a bunch of different changes.  Individual
    commit titles follow:

    i965/fs: Always 2-align registers SIMD16 for gen <= 5

    i965/fs: Use the register width when applying offsets

       This reworks both byte_offset() and offset() to be more intelligent.
       The byte_offset() function now supports offsets bigger than 32. The
       offset() function uses the byte_offset() function together with the
       register width and the type size to offset the register by the correct
       amount.

    i965/fs: Change regs_read to be in hardware registers

    i965/fs: Change regs_written to be actual hardware registers

    i965/fs: Properly handle register widths in LOAD_PAYLOAD

       The LOAD_PAYLOAD instruction is a bit special because it collects a
       bunch of registers (with possibly different widths) into a single
       payload block.  Once the payload is constructed, it's treated as a
       single block of data and most of the information such as register widths
       doesn't matter anymore.  In particular, the offset of any particular
       source register is the accumulation of the sizes of the previous source
       registers.

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