[Bug 90895] [BSW regression] SynMark2_v6_0_0_OglBatch0 to OglBatch4 performance reduce by ~23%

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=90895

--- Comment #2 from ye.tian <yex.tian at intel.com> ---
By bisected, shows the first mesa commit is b639ed2.

commit b639ed2f1b170d1184c6d94c88c826c51ffc8726
Author:     Ben Widawsky <benjamin.widawsky at intel.com>
AuthorDate: Thu Jun 4 23:59:23 2015 -0700
Commit:     Ben Widawsky <benjamin.widawsky at intel.com>
CommitDate: Fri Jun 5 14:25:47 2015 -0700

    i965: Add gen8 fast clear perf debug

    In an ideal world I would just implement this instead of adding the perf
debug.
    There are some errata involved which lead me to believe it won't be so
simple as
    flipping a few bits.

    There is room to add a thing for Gen9s flexibility, but since I am actively
    working on that I have opted to ignore it.

    Example:
    Multi-LOD fast clear - giving up (256x128x8).

    v2: Use braces for if statements because they are multiple lines (Ken)

    Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

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