[Bug 90520] New: Register spilling clobbers registers used elsewhere in the shader

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=90520

            Bug ID: 90520
           Summary: Register spilling clobbers registers used elsewhere in
                    the shader
           Product: Mesa
           Version: git
          Hardware: Other
                OS: All
            Status: NEW
          Severity: normal
          Priority: medium
         Component: Drivers/DRI/i965
          Assignee: idr at freedesktop.org
          Reporter: neil at linux.intel.com
        QA Contact: intel-3d-bugs at lists.freedesktop.org

When a register is spilled it will emit a SHADER_OPCODE_GEN4_SCRATCH_WRITE
pseudo opcode whenever it writes to the spilled register. When the code for
this opcode is generated it will sneak in a write to MRF registers 14 and 15 in
order to set up the message. On Gen7+ these MRF registers are mapped to GRF
registers 126 and 127. The trouble is that the register allocator doesn't know
that the pseudo opcode does these writes so it will happily allocate g126-g127
to something else and then it will get clobbered when the scratch write is
done.

I noticed this because there are a bunch of varying-packing Piglit tests
failing on Skylake. These get compiled very badly and end up using an excessive
amount of virtual registers. Presumably the tests would also fail on Broadwell
which also uses SIMD8 for vertex shaders. However I think the general problem
presumably exists everywhere and even on Gen6 it might be possible to clobber
an MRF register that is used elsewhere.

An example of a test that fails on Skylake is this:

piglit/bin/varying-packing-simple float array -auto -fbo

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