[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

            Bug ID: 92760
           Summary: Add FP64 support to the i965 shader backends
           Product: Mesa
           Version: unspecified
          Hardware: All
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: medium
         Component: Drivers/DRI/i965
          Assignee: idr at freedesktop.org
          Reporter: jason at jlekstrand.net
        QA Contact: intel-3d-bugs at lists.freedesktop.org

We've had a variety of people take a crack at this over the last year or two
and haven't actually gotten there yet.  I'm making this bug as a place to put
notes for the next person to pick it up.  Connor Abbott started on this towards
the end of this summer but there's still more work to do.  The best place to
pick up would probably be with his branch which can be found here:

http://cgit.freedesktop.org/~cwabbott0/mesa/log/?h=i965-fp64-v2

With this branch, most of the core NIR bits are in place and most of the i965
fs backend code is in place but there's still more to do:

 1) Review core NIR bits (Probably Jason)

 2) Write a bit-width well-definedness validator for nir_algebraic (Probably
Jason or Connor)

 3) Write piglit tests for and fix up Uniform alignment issues.  The hardware
requires that 64-bit things be 64-bit aligned and we're doing nothing right now
to ensure that.

 4) Implement NIR lowering of ftrunc and use that to implement fround etc.

 5) Write more tests.  Right now, the piglit tests for fp64 basically only test
the math operations.  There are many other things that need testing such as
uniform packing, UBOs, SSBOs, pack/unpack operations, and whatever other
interactions need testing.  One of the issues Connor ran into was that the
"simplest" tests were doing double-precision operations like sqrt that were
lowered lots of operations and made it very hard to debug simple issues.

 6) Implement a NIR pass to lower double-precision vec4 operations to vec2
operations for use in the vec4 backend.

 7) Get fp64 working in the vec4 backend.  The vec4 backend can only work with
doubles as vec2's; hence the splitting pass in (6)

There's probably more I've missed here but this is what I remember.

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