[Bug 92760] Add FP64 support to the i965 shader backends

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Mon Apr 4 09:19:12 UTC 2016


--- Comment #70 from Iago Toral <itoral at igalia.com> ---
Created attachment 122690
  --> https://bugs.freedesktop.org/attachment.cgi?id=122690&action=edit
Sample test showcasing non-uniform control flow problems in align16

I forgot to attach this. The test executes non-uniform control flow with DF
operations in a vertex shader. If we run this in gen7, it will execute in
align16 mode.

The test renders a quad and is expected to produce 3 red vertices and 1 green
vertex, but the result is 2 red and 2 green, which means that one vertex is
taking the incorrect branch of the conditional, confirming Curro's point that
we have an execmask problem. The test produces the expected result in gen8
because it runs VS in scalar mode.

You are receiving this mail because:
You are the QA Contact for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/intel-3d-bugs/attachments/20160404/37d27c4d/attachment.html>

More information about the intel-3d-bugs mailing list