[Bug 92760] Add FP64 support to the i965 shader backends

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92760

--- Comment #79 from Iago Toral <itoral at igalia.com> ---
(In reply to Francisco Jerez from comment #77)
> (In reply to Iago Toral from comment #76)
> > (In reply to Francisco Jerez from comment #73)
> > > (In reply to Jason Ekstrand from comment #72)
> > > > (In reply to Iago Toral from comment #66)
> > > > > Jason, Connor:
> > > > > 
> > > > > last week Curro spent some time looking at our fp64 branch and testing some
> > > > > things and we have been discussing some aspects of the hardware in fp64 that
> > > > > are not all that well documented (or not even documented at all :)) and that
> > > > > may have some important implications in the implementation, specifically for
> > > > > the vec4 backend.
> > > > >
> > > > > Opinions?
> > > > 
> > > > Short version:
> > > > 
> > > > a) The hardware is busted.
> > > > b) I think Curro knows what he's talking about.  :-)
> > > > 
> > > > Longer version:
> > > > 
> > > > I see a couple of options here:  One is to just scalarize all double stuff. 
> > > > On Ivy Bridge, I think you would also have to double up instructions, one
> > > > for each half.  It's not a great option from the perspective of performance
> > > > but is perhaps the easiest to implement.
> > > > 
> > > > The second option is what Curro's suggesting where you try and use the
> > > > hardware as much as possible and fall back to nasty things only when you
> > > > have to.  Unfortunately, this is going to cause a lot of pain in the
> > > > generator because suddenly lots of stuff may become align1 at least on IVB.
> > > > 
> > > Just a short comment on this point: I don't think IVB will be much worse.
> > > From the functional point of view it's not that much different from HSW+,
> > > its primary limitation is that Align16 FP64 instructions can't do more than
> > > one dvec4 at a time, but that's easily solvable by hooking up the SIMD width
> > > lowering pass (in addition to the swizzle and writemask lowering pass that
> > > could be used on later gens), because NibCtrl behaves as expected on FP64
> > > Align16 instructions even on IVB thankfully.
> > 
> > I think there is still a problem with this: the fact that NibCtrl only works
> > with DF instructions, but we would still need to deal with UD access to DF
> > data... wouldn't that be broken in this case?
> 
> Sure, but that problem is fully orthogonal to IVB's level of support for
> FP64 in Align16 mode and needs to be addressed for later platforms anyway. 
> IVB's limitation on the execution size is specific to double precision types
> in Align16 mode, so if you do either Align1 or UD execution type you avoid
> the problem.

I see, yeah, I suppose we should be safe then.

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