[Bug 105440] GEN7: rendering issue on citra

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=105440

--- Comment #3 from vadym <vadym.shovkoplias at globallogic.com> ---
I also run the test with INTEL_DEBUG=vs option with the patch (comment 2) and
without it and got following result:

@@ -76,20 +76,16 @@ impl main {
        vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
        vec4 32 ssa_2 = intrinsic load_input (ssa_1) () (0, 0) /* base=0 */ /*
component=0 */   /* in_0 */
        vec4 32 ssa_3 = intrinsic load_uniform (ssa_1) () (0, 64) /* base=0 */
/* range=64 */   /* parameters */
-       vec4 32 ssa_4 = fdot_replicated4 ssa_2, ssa_3
+       r4.x = fdot_replicated4 ssa_2, ssa_3
        vec1 32 ssa_5 = load_const (0x00000010 /* 0.000000 */)
        vec4 32 ssa_6 = intrinsic load_uniform (ssa_5) () (0, 64) /* base=0 */
/* range=64 */   /* parameters */
-       vec4 32 ssa_7 = fdot_replicated4 ssa_2, ssa_6
+       r4.y = fdot_replicated4 ssa_2, ssa_6
        vec1 32 ssa_8 = load_const (0x00000020 /* 0.000000 */)
        vec4 32 ssa_9 = intrinsic load_uniform (ssa_8) () (0, 64) /* base=0 */
/* range=64 */   /* parameters */
-       vec4 32 ssa_10 = fdot_replicated4 ssa_2, ssa_9
+       r4.z = fdot_replicated4 ssa_2, ssa_9
        vec1 32 ssa_11 = load_const (0x00000030 /* 0.000000 */)
        vec4 32 ssa_12 = intrinsic load_uniform (ssa_11) () (0, 64) /* base=0
*/ /* range=64 */ /* parameters */
-       vec4 32 ssa_13 = fdot_replicated4 ssa_2, ssa_12
-       r4.x = imov ssa_4.x
-       r4.y = imov ssa_7.x
-       r4.z = imov ssa_10.x
-       r4.w = imov ssa_13.x
+       r4.w = fdot_replicated4 ssa_2, ssa_12
        vec4 32 ssa_15 = intrinsic load_input (ssa_1) () (1, 0) /* base=1 */ /*
component=0 */
        vec4 32 ssa_16 = intrinsic load_input (ssa_1) () (2, 0) /* base=2 */ /*
component=0 */  /* in_2 */
        r5.x = imov ssa_16.x

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