[Bug 109517] [GEN9+] 14-24% perf drop in SynMark2 v7 CSDof

bugzilla-daemon at freedesktop.org bugzilla-daemon at freedesktop.org
Tue Feb 12 09:30:00 UTC 2019


--- Comment #5 from Eero Tamminen <eero.t.tamminen at intel.com> ---
(In reply to Jason Ekstrand from comment #4)
> Ugh...  I'm not really sure what we should do about this one.  Mark's bisect
> is exactly correct.  I've looked at the shaders, and there seems to be two
> issues:
>  1) There's one SIMD8 shader which schedules massively differently for no
> apparent reason.
>  2) There's a SIMD16 shader which starts spilling way more than it was before

Based on your comment below I assume that SIMD8 shader also got worse, but does
it also spill?  I.e. is the bad behavior limited to spilling shaders?

> In both cases, I have no idea why it's happening beyond the fact that our
> current RA and scheduling has rather random behaviour at times.  Using SENDS
> should only ever decrease register pressure and increase RA freedom because
> it no longer has to build the message into a single hunk and can just send
> the two bits (address and data) separately.
> As I said in the commit message I have another (unfortunately not public
> yet) customer workload where the opposite happens and using SENDS decreases
> spilling and improves performance by 2x.

SENDS support is needed performance feature.  If the current implementation
improves things more than it regresses, and especially if the improving cases
are more important like here, I think letting regression in for the release is

There could be some meta-bug about the RA / scheduler related issues which this
(and e.g. bugs about bad sampler fetch scheduling) would link to though.

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