[Bug 109985] [SNB] INTEL_DEBUG=nohiz is likely broken for depth/stencil buffers

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=109985

--- Comment #12 from asimiklit <andrey.simiklit at gmail.com> ---
(In reply to Nanley Chery from comment #0)
> For SNB, INTEL_DEBUG=nohiz seems to be broken in two places:
> 
> 1. In miptree_create() in intel_mipmap_tree.c. Trying to create a
> depth/stencil buffer will cause a depth miptree to be created without
> stencil.

As far as found this code disallows us to create combined depth/stencil on SNB:
   mesa_format mt_fmt = format;
   if (!_mesa_is_format_color_format(format) && devinfo->gen >= 6) {
      /* Fix up the Z miptree format for how we're splitting out separate
       * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
       */
      mt_fmt = intel_depth_format_for_depthstencil_format(format);
   }

   Note: This code just replaces MESA_FORMAT_Z24_UNORM_S8_UINT by
MESA_FORMAT_Z24_UNORM_X8_UINT
         but in this case 'mt_surf_usage' does not return a
ISL_SURF_USAGE_STENCIL_BIT and that leads to
         an assertion: assert(src_surf->surf->usage &
ISL_SURF_USAGE_STENCIL_BIT); in a blorp_blit function.
         PS: Actually I didn't check if this assertion actually matter.

But just avoiding of this code doesn't make us happy too (
Because we fail a choosing of a surf tiling method and "isl_surf_choose_tiling"
always returns false.

Now I am investigates a SNB PRM for the valid combinations of tiling methods
with combined depth/stencil.

Any advices or suggestions are welcome :)

> 
> 2. In isl_genX(emit_depth_stencil_hiz_s) in isl_emit_depth_stencil.c.
> Emitting a depth/stencil buffer instruction will unconditionally force HiZ
> on.

It happens because we create a separate stencil here regardless "nohiz" flag
(under SNB we always jump into 'true' branch in the following code):

   if (screen->devinfo.has_hiz_and_separate_stencil) {
      rb = intel_create_private_renderbuffer(screen,
                                             MESA_FORMAT_Z24_UNORM_X8_UINT,
                                             num_samples);
      _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
      rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_S_UINT8,
                                             num_samples);
      _mesa_attach_and_own_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
   } else {
      /*
       * Use combined depth/stencil. Note that the renderbuffer is
       * attached to two attachment points.
       */
      rb = intel_create_private_renderbuffer(screen,
                                             MESA_FORMAT_Z24_UNORM_S8_UINT,
                                             num_samples);
      _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
      _mesa_attach_and_reference_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
   }

A separate stencil forces us to emit a "Hierarchical Depth Buffer Enable" as a
TRUE because of:
   SNB PRM Vol 2 Part 1 about field 'Separate Stencil Buffer Enable':
   [DevSNB]: This field must be set to the same value (enabled or disabled) as
Hierarchical Depth Buffer Enable

So looks like we need to create a combined depth/stencil there for
has_separate_stencil = false
case but as you mentioned above we unable to create combined depth/stencil due
to issue 1.

> 
> I haven't tested/verified these observations.
> 
> mesa version: ae77f1236862e73c1ac250898924c648d481bda4

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/intel-3d-bugs/attachments/20190329/0579243b/attachment.html>