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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - Add FP64 support to the i965 shader backends"
href="https://bugs.freedesktop.org/show_bug.cgi?id=92760#c65">Comment # 65</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - Add FP64 support to the i965 shader backends"
href="https://bugs.freedesktop.org/show_bug.cgi?id=92760">bug 92760</a>
from <span class="vcard"><a class="email" href="mailto:itoral@igalia.com" title="Iago Toral <itoral@igalia.com>"> <span class="fn">Iago Toral</span></a>
</span></b>
<pre><span class="quote">> fs_reg setup_imm_df(double v) {
> vgrf<double> tmp;
> tmp = retype(tmp, unsigned)
>
> vgrf<double> v_low, v_high;
> v_low = retype(tmp, unsigned)
> v_high = retype(tmp, unsigned)
>
> mov(v_low, brw_imm_ud(low32(v)));
> mov(v_high, brw_imm_ud(high32(v)));</span >
Just to be clear, these two MOVs above move to both reg_offset 0 and reg_offset
1, so they write both SIMD registers allocated for both v_low and v_high.
<span class="quote">> mov(stride(tmp, 2), stride(v_low, 2));
> mov(stride(horiz_offset(tmp, 1), 2), stride(v_high, 2));
>
> return retype(tmp, double)
> }</span ></pre>
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