<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - Add FP64 support to the i965 shader backends" href="https://bugs.freedesktop.org/show_bug.cgi?id=92760#c87">Comment # 87</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - Add FP64 support to the i965 shader backends" href="https://bugs.freedesktop.org/show_bug.cgi?id=92760">bug 92760</a> from <a class="email" href="mailto:itoral@igalia.com" title="Iago Toral <itoral@igalia.com>"> Iago Toral</a> <pre>(In reply to Iago Toral from <a href="show_bug.cgi?id=92760#c86">comment #86</a>) > (In reply to Francisco Jerez from <a href="show_bug.cgi?id=92760#c84">comment #84</a>) > > (In reply to Iago Toral from <a href="show_bug.cgi?id=92760#c83">comment #83</a>) > > >[...] > > >> due to an instruction decompression bug (or feature?) that causes it > > >> to increment the register offset of the second half by a fixed amount > > >> of one GRF regardless of the vertical stride. The end result is the > > >> instruction behaves as if the source had the logical region > > >> r0.0<4>.xyxy (where the swizzles are actual logical swizzles, i.e. in > > >> units of whole 64bit components) and we have managed to get the ZW > > >> components to cross the vec2 boundary and read the XY components from > > >> the first oword of the register. > > > > > > For the sake of completeness, one idea that we discussed was to try and exploit > > > this to access components Z/W like: > > > > > > r0.2<0,2,1>.xyzw:df > > > > > > That is, we start the region at offset 16B (i.e. right where Z for the first > > > vertex starts) and then use the vstride=0 trick to read past the first GRF and > > > access the Z/W data for the second vertex in the SIMD4x2 execution. > > > > > > I have to say, however, that I tried to do some quick tests to verify that this > > > actually works and it didn't for me. I think in this case we might be violating > > > a few hardware restrictions because: > > > > > > > I'm pretty sure I tried that on HSW at some point and it worked fine for > > me, I'll see if I can dig up the exact assembly code I used. > > > Don't worry, I am not 100% certain that this is the example I tried. Maybe I > was trying uniforms or something slightly different. Let me try to hit the > problem again and if I do then we can check what is going on with it. Ok, so I got back to this and it does work fine, the problem I was having before is that I was using a dvec3 uniform and due to the vstride=0 bug we need to use SIMD splitting to source from that. We haven't implemented that yet and so far I was using a hack to copy the uniform to a vgrf and source from that instead so I could test some things in the meantime, but when I wrote that code I did only consider double and dvec2 uniforms so I had to update the hack to deal with dvec3 uniforms too.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>