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      <base href="https://bugs.freedesktop.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - skylake: page fault accessing address 0"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=101283">101283</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>skylake: page fault accessing address 0
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>Mesa
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>17.0
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>Other
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Drivers/Vulkan/intel
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>cstout@chromium.org
          </td>
        </tr>

        <tr>
          <th>QA Contact</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>jason@jlekstrand.net
          </td>
        </tr></table>
      <p>
        <div>
        <pre>The function blorp_emit_gen8_hiz_op contains a pipe control operation that has
only the WriteImmediateData bit set.  It doesn't specify an address, so this
results in a store to address 0.

a) What is this pipe control for?  I don't see the need for it in the docs.

>From what I can see, the docs for 3DSTATE_WM_HZ_OP say: "As this command
generates an implicit rectangle, SW must make sure any MMIO register writes
following WM_HZ_OP must be preceded by PIPE_CONTROL with Command Streamer Stall
Enable bit set."

In the code there's a following PIPECONTROL with depth_stall and depth flush
bits set, which corresponds to the docs in the section 'Depth Buffer Clear'.

b) How is it not a problem to emit a pipecontrol that writes to address 0?

Thanks.</pre>
        </div>
      </p>


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