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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [BYT] ES31-CTS.functional.copy_image.non_compressed.viewclass_96_bits.rgb32f_rgb32f"
href="https://bugs.freedesktop.org/show_bug.cgi?id=101910#c7">Comment # 7</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [BYT] ES31-CTS.functional.copy_image.non_compressed.viewclass_96_bits.rgb32f_rgb32f"
href="https://bugs.freedesktop.org/show_bug.cgi?id=101910">bug 101910</a>
from <span class="vcard"><a class="email" href="mailto:topi.pohjolainen@intel.com" title="Topi Pohjolainen <topi.pohjolainen@intel.com>"> <span class="fn">Topi Pohjolainen</span></a>
</span></b>
<pre>I made originally a mistake in comparing batch buffer dumps. There is a valign
2 vs.4 difference in one of the surfaces but this is actually insignificant to
the problem in hand. Whereas ISL opts to use valign of 2 for X-tiled RGBA_UNORM
old miptree logic chose 4. Both seem to work, ISL just uses a little less
space.
The difference in case of RGB32F is tiling - ISL falls back to X-tiling while
old i965 uses Y-tiling. The last hack of mine changed this allowing ISL to keep
on using Y-tiling. The fact that it changed valign from 2 to 4 is actually
wrong but for some reason didn't upset the hardware.</pre>
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