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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=103115">103115</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>Mesa
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>git
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>Other
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Drivers/DRI/i965
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>mark.a.janes@intel.com
          </td>
        </tr>

        <tr>
          <th>QA Contact</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>This test and three others regressed at 
mesa 2572c2771d0cab0b9bc489d354ede44dfc88547b
Author:     Matt Turner <<a href="mailto:mattst88@gmail.com">mattst88@gmail.com</a>>
i965: Validate "Special Requirements for Handling Double Precision Data Types"

I did not implement:

   CNL's restriction on 64-bit int + align16, because I don't think
   we'll ever use this combination regardless of hardware generation.

   The restriction on immediate DF -> F conversions, because there's no
   reason to ever generate that, and I don't even know how DF -> F
   conversions are supposed to work in Align16 since (1) the dst stride
   must be 1, but (2) the dst stride would have to be 2 for src and dst
   strides to be aligned.

---------------------------------------------
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_uint64
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_uint64
+dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64

deqp-vk:
/home/jenkins/workspace/Leeroy_2/repos/mesa/src/intel/compiler/brw_fs_generator.cpp:2203:
int fs_generator::generate_code(const cfg_t*, int): Assertion `validated'
failed.</pre>
        </div>
      </p>


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