<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails" href="https://bugs.freedesktop.org/show_bug.cgi?id=103007#c1">Comment # 1</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails" href="https://bugs.freedesktop.org/show_bug.cgi?id=103007">bug 103007</a> from <a class="email" href="mailto:itoral@igalia.com" title="Iago Toral <itoral@igalia.com>"> Iago Toral</a> <pre>Fixed in master with: commit 8620f7ebbc763dc1bbbc825d31cacfdd84433e05 Author: Iago Toral Quiroga <<a href="mailto:itoral@igalia.com">itoral@igalia.com</a>> Date: Wed Nov 29 10:50:42 2017 +0100 i965/vec4: use a temp register to compute offsets for pull loads 64-bit pull loads are implemented by emitting 2 separate 32-bit pull load messages, where the second message loads from an offset at +16B. That addition of 16B to the original offset should not alter the original offset register used as source for the pull load instruction though, since the compiler might use that same offset register in other instructions (for example, for other pull loads in the shader code that take that same offset as reference). If the pull load is 32-bit then we only need to emit one message and we don't need to do offset calculations, but in that case the optimizer should be able to drop the redundant MOV. Fixes the following test on Haswell: KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components Reviewed-by: Matt Turner <<a href="mailto:mattst88@gmail.com">mattst88@gmail.com</a>> Bugzilla: <a class="bz_bug_link bz_status_NEW " title="NEW - [OpenGL CTS] [HSW] KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails" href="show_bug.cgi?id=103007">https://bugs.freedesktop.org/show_bug.cgi?id=103007</a></pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>