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<base href="https://bugs.freedesktop.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [CI][GLK] Ubuntu 18.04 (pre-release) fails piglit variable-indexing tests"
href="https://bugs.freedesktop.org/show_bug.cgi?id=106148">106148</a>
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<th>Summary</th>
<td>[CI][GLK] Ubuntu 18.04 (pre-release) fails piglit variable-indexing tests
</td>
</tr>
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<th>Product</th>
<td>Mesa
</td>
</tr>
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<th>Version</th>
<td>18.0
</td>
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<th>Hardware</th>
<td>x86-64 (AMD64)
</td>
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<th>OS</th>
<td>Linux (All)
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>medium
</td>
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<th>Component</th>
<td>Drivers/DRI/i965
</td>
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<th>Assignee</th>
<td>intel-3d-bugs@lists.freedesktop.org
</td>
</tr>
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<th>Reporter</th>
<td>tomi.p.sarvela@intel.com
</td>
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<th>QA Contact</th>
<td>intel-3d-bugs@lists.freedesktop.org
</td>
</tr></table>
<p>
<div>
<pre>Hi,
We're adding piglit regression testing to Intel-GFX-CI. When running our
testsets to get a good green baseline, an issue was found with Gemini Lake NUC:
it fails a bunch of tests that didn't fail on SKL (6600) or HSW (4770r) on
DRM-Tip kernels.
Hardware is Intel NUC7CJYH (J4005) 2 cores and 2x4GB memory
Distro is freshly installed Ubuntu 18.04 with todays updates, and kernel / mesa
version reflects that:
wflinfo -p gbm -a gl: Mesa 18.0.0-rc5
uname -a: Linux 4.15.0-12-generic or (for example) 4.17.0-rc1-CI-CI_DRM_4069
Example of the piglit invocation:
$ ./piglit run tests/gpu ~/results -p gbm -t
spec@arb_tessellation_shader@execution@variable-indexing@
Specific information can be gleaned from
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/piglit-issues.html">https://intel-gfx-ci.01.org/tree/drm-tip/piglit-issues.html</a>
CI_DRM_4069 is the last kernel without all the blacklisting on.
Tests below fail on all hosts with default Ubuntu kernel, and
they fail on GLK when using DRM-Tip kernel (this needs confirmation):
spec@arb_tessellation_shader@execution@1in-1out
spec@arb_tessellation_shader@execution@dmat-vs-gs-tcs-tes
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-float-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-vec2-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-vec3-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-vec4-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-float-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-vec2-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-vec3-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-vec4-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-float-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-vec2-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-vec3-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-vec4-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-float-index-wr-before-tcs
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec2-index-wr-before-tcs
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec4-index-wr-before-tcs
<a href="mailto:spec@glsl-1.50">spec@glsl-1.50</a>@execution@geometry@end-primitive
<a href="mailto:spec@glsl-1.50">spec@glsl-1.50</a>@execution@geometry@max-input-components
<a href="mailto:spec@glsl-1.50">spec@glsl-1.50</a>@execution@variable-indexing@gs-input-array-vec3-index-rd
<a href="mailto:spec@glsl-1.50">spec@glsl-1.50</a>@execution@variable-indexing@gs-input-array-vec4-index-rd
<a href="mailto:spec@glsl-1.50">spec@glsl-1.50</a>@execution@variable-indexing@vs-output-array-vec3-index-wr-before-gs
<a href="mailto:spec@glsl-1.50">spec@glsl-1.50</a>@gs-max-output-components
Note that Ubuntu 18.04 and the mesa version is still moving around, and kernel
is just-released -RC1, so this could be just a fluke on our systems. I'll open
the bug anyway for investigation because reproduction should be easy.</pre>
</div>
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