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<body><span class="vcard"><a class="email" href="mailto:kenneth@whitecape.org" title="Kenneth Graunke <kenneth@whitecape.org>"> <span class="fn">Kenneth Graunke</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [G965] Some objects in Neverwinter Nights Linux version not displayed correctly"
href="https://bugs.freedesktop.org/show_bug.cgi?id=13728">bug 13728</a>
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<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Resolution</td>
<td>---
</td>
<td>FIXED
</td>
</tr>
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<td style="text-align:right;">Status</td>
<td>NEW
</td>
<td>RESOLVED
</td>
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [G965] Some objects in Neverwinter Nights Linux version not displayed correctly"
href="https://bugs.freedesktop.org/show_bug.cgi?id=13728#c29">Comment # 29</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [G965] Some objects in Neverwinter Nights Linux version not displayed correctly"
href="https://bugs.freedesktop.org/show_bug.cgi?id=13728">bug 13728</a>
from <span class="vcard"><a class="email" href="mailto:kenneth@whitecape.org" title="Kenneth Graunke <kenneth@whitecape.org>"> <span class="fn">Kenneth Graunke</span></a>
</span></b>
<pre>Hi Sven, Vasyl,
TIS-100 and other Gen4-5 misrendering with SIMD16 should be fixed with the
following commit on master. Sorry this took so horribly long. :(
commit 08a5c395abdafd0d7556060596f78c238b4a989f
Author: Kenneth Graunke <<a href="mailto:kenneth@whitecape.org">kenneth@whitecape.org</a>>
Date: Thu Aug 2 15:02:18 2018 -0700
intel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.
When the SIMD16 Gen4-5 fragment shader payload contains source depth
(g2-3), destination stencil (g4), and destination depth (g5-6), the
single register of stencil makes the destination depth unaligned.
We were generating this instruction in the RT write payload setup:
mov(16) m14<1>F g5<8,8,1>F { align1 compr };
which is illegal, instructions with a source region spanning more than
one register need to be aligned to even registers. This is because the
hardware implicitly does (nr | 1) instead of (nr + 1) when splitting the
compressed instruction into two mov(8)'s.
I believe this would cause the hardware to load g5 twice, replicating
subspan 0-1's destination depth to subspan 2-3. This showed up as 2x2
artifact blocks in both TIS-100 and Reicast.
Normally, we rely on the register allocator to even-align our virtual
GRFs. But we don't control the payload, so we need to lower SIMD widths
to make it work. To fix this, we teach lower_simd_width about the
restriction, and then call it again after lower_load_payload (which is
what generates the offending MOV).
Fixes: 8aee87fe4cce0a883867df3546db0e0a36908086 (i965: Use SIMD16 instead
of SIMD8 on Gen4 when possible.)
Bugzilla: <a class="bz_bug_link
bz_status_CLOSED bz_closed"
title="CLOSED FIXED - Dual-Core CPU E5500 / G45: RetroArch with reicast core results in corrupted graphics"
href="show_bug.cgi?id=107212">https://bugs.freedesktop.org/show_bug.cgi?id=107212</a>
Bugzilla: <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [G965] Some objects in Neverwinter Nights Linux version not displayed correctly"
href="show_bug.cgi?id=13728">https://bugs.freedesktop.org/show_bug.cgi?id=13728</a>
Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>>
Tested-by: Diego Viola <<a href="mailto:diego.viola@gmail.com">diego.viola@gmail.com</a>></pre>
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