<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [GLK BXT BSW] Assertion in piglit.spec.arb_gpu_shader_fp64.execution.built-in-functions.vs-sign-sat-neg-abs" href="https://bugs.freedesktop.org/show_bug.cgi?id=108319#c3">Comment # 3</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [GLK BXT BSW] Assertion in piglit.spec.arb_gpu_shader_fp64.execution.built-in-functions.vs-sign-sat-neg-abs" href="https://bugs.freedesktop.org/show_bug.cgi?id=108319">bug 108319</a> from <a class="email" href="mailto:idr@freedesktop.org" title="Ian Romanick <idr@freedesktop.org>"> Ian Romanick</a> <pre>To my surprise, the culprit is: commit a68dd47b911053995ae387afcdc7fffe82e57420 Author: Ian Romanick <<a href="mailto:ian.d.romanick@intel.com">ian.d.romanick@intel.com</a>> Date: Sun Sep 9 13:40:02 2018 -0700 nir/algebraic: Simplify fsat of fsign These allows us to not support fsign.sat in the Intel compiler backend, and that will simplify some later changes. No shader-db changes on any Intel platform. Signed-off-by: Ian Romanick <<a href="mailto:ian.d.romanick@intel.com">ian.d.romanick@intel.com</a>> Reviewed-by: Thomas Helland <<a href="mailto:thomashelland90@gmail.com">thomashelland90@gmail.com</a>> Looking at the output from the EU validator, I think the problem is the b2f generates a 32-bit result instead of a 64-bit result: Native code for unnamed vertex shader GLSL3 SIMD8 shader: 35 instructions. 0 loops. 188 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 560 to 464 bytes (17%) START B0 (188 cycles) mov(8) g8<1>Q 0Q { align1 1Q }; mov(8) g119<1>UD g1<8,8,1>UD { align1 WE_all 1Q compacted }; mov(8) g120<1>F g4<8,8,1>F { align1 1Q compacted }; mov(8) g121<1>F g5<8,8,1>F { align1 1Q compacted }; mov(8) g122<1>F g6<8,8,1>F { align1 1Q compacted }; mov(8) g123<1>F g7<8,8,1>F { align1 1Q compacted }; mov(8) g126<1>F [0F, 0F, 0F, 0F]VF { align1 1Q compacted }; mov(8) g127<1>F 1F { align1 1Q }; cmp.l.f0(8) g4<1>DF g8<4,4,1>DF -(abs)g2<0,1,0>DF { align1 1Q }; cmp.l.f0(8) g6<1>DF g8<4,4,1>DF -(abs)g2.1<0,1,0>DF { align1 1Q }; cmp.l.f0(8) g10<1>DF g8<4,4,1>DF -(abs)g2.2<0,1,0>DF { align1 1Q }; cmp.l.f0(8) g12<1>DF g8<4,4,1>DF -(abs)g2.3<0,1,0>DF { align1 1Q }; mov(8) g4<1>D g4<8,4,2>UD { align1 1Q }; mov(8) g7<1>D g6<8,4,2>UD { align1 1Q }; mov(8) g2<1>D g10<8,4,2>UD { align1 1Q }; mov(8) g5<1>DF -g4<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit mov(8) g4<1>D g12<8,4,2>UD { align1 1Q }; mov(8) g7<1>DF -g7<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit mov(8) g11<1>DF -g2<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit mov(8) g13<1>DF -g4<4,4,1>D { align1 1Q }; ERROR: Source and destination horizontal stride must equal and a multiple of a qword when the execution type is 64-bit cmp.nz.f0(8) g7<1>DF g7<4,4,1>DF g3.1<0,1,0>DF { align1 1Q }; cmp.nz.f0(8) g4<1>DF g5<4,4,1>DF g3<0,1,0>DF { align1 1Q }; mov(8) g2<1>D g7<8,4,2>UD { align1 1Q }; cmp.nz.f0(8) g6<1>DF g11<4,4,1>DF g3.2<0,1,0>DF { align1 1Q }; mov(8) g4<1>D g4<8,4,2>UD { align1 1Q }; cmp.nz.f0(8) g8<1>DF g13<4,4,1>DF g3.3<0,1,0>DF { align1 1Q }; mov(8) g3<1>D g6<8,4,2>UD { align1 1Q }; or(8) g2<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 1Q compacted }; mov(8) g4<1>D g8<8,4,2>UD { align1 1Q }; or(8) g2<1>UD g2<8,8,1>UD g3<8,8,1>UD { align1 1Q compacted }; or(8) g2<1>UD g2<8,8,1>UD g4<8,8,1>UD { align1 1Q compacted }; mov(8) g124<1>F -g2<8,8,1>D { align1 1Q compacted }; not(8) g4<1>D g2<8,8,1>D { align1 1Q compacted }; mov(8) g125<1>F -g4<8,8,1>D { align1 1Q compacted }; send(8) null<1>F g119<8,8,1>F urb 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; END B0</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>