<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_REOPENED " title="REOPENED - [GEN8+] up to 10% perf drop on several 3D benchmarks" href="https://bugs.freedesktop.org/show_bug.cgi?id=107510#c16">Comment # 16</a> on <a class="bz_bug_link bz_status_REOPENED " title="REOPENED - [GEN8+] up to 10% perf drop on several 3D benchmarks" href="https://bugs.freedesktop.org/show_bug.cgi?id=107510">bug 107510</a> from <a class="email" href="mailto:eero.t.tamminen@intel.com" title="Eero Tamminen <eero.t.tamminen@intel.com>"> Eero Tamminen</a> <pre>(In reply to Timothy Arceri from <a href="show_bug.cgi?id=107510#c15">comment #15</a>) > Splitting and/or vectorising FS inputs seems to case the scheduler to vary > wildly. I'm seeing up to +/-50% swings in cycle counts in both directions. I don't trust scheduler cycle counts much for shaders doing sampling. Texture fetches have most impact on perf/cycles, but when I last looked at this: * Cycle counts are obviously wrong for SIMD32 (when comparing reported cycle changes to the actual perf change), so I don't think it takes latency compensation from threading properly into account * I'm not sure how well it takes cache impact for texture fetches into account either (on average first fetch for given sampler takes more cycles than successive ones, and grouping few fetches to same sampler together and distancing such groups from each other, uses less cycles as that minimizes cache trashing. Windows driver produced shader assembly looks on average noticeably better in this respect than i965 produced assembly) > I'm not sure what to do about this. IMHO i965 instruction scheduler cycle accounting and texture fetch scheduling would need to be improved. Not sure who can do that though. I think that for this bug, your patch is enough though.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the QA Contact for the bug.</li> </ul> </body> </html>