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    <head>
      <base href="https://bugs.freedesktop.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Image load store regressions"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=109056">109056</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Image load store regressions
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>Mesa
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>Other
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Keywords</th>
          <td>bisected, regression
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Drivers/DRI/i965
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>mark.a.janes@intel.com
          </td>
        </tr>

        <tr>
          <th>QA Contact</th>
          <td>intel-3d-bugs@lists.freedesktop.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Vulkan tests regresson on i965:

dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgb_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgb_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgba_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc1_rgba_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc4_snorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.basic.image_store.bc4_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgb_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgb_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgba_srgb_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc1_rgba_unorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc4_snorm_block.r16g16b16a16_sfloat
dEQP-VK.image.texel_view_compatible.compute.extended.image_store.bc4_unorm_block.r16g16b16a16_sfloat

In the output for these tests:
error: src->ssa->num_components == num_components
(../src/compiler/nir/nir_validate.c:206)

Bisected to:
06fbcd2cd5cc5702c9039c26d20082a99bc157bf
Author:     Eric Anholt <<a href="mailto:eric@anholt.net">eric@anholt.net</a>>

intel: Simplify the half-float packing in image load/store lowering.

This was noted by Jason in review when I tried to make a helper for the
old path.

Reviewed-by: Jason Ekstrand <<a href="mailto:jason@jlekstrand.net">jason@jlekstrand.net</a>></pre>
        </div>
      </p>


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