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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [i965] Downward causes GPU hangs and misrendering on Haswell"
href="https://bugs.freedesktop.org/show_bug.cgi?id=104297#c40">Comment # 40</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [i965] Downward causes GPU hangs and misrendering on Haswell"
href="https://bugs.freedesktop.org/show_bug.cgi?id=104297">bug 104297</a>
from <span class="vcard"><a class="email" href="mailto:kenneth@whitecape.org" title="Kenneth Graunke <kenneth@whitecape.org>"> <span class="fn">Kenneth Graunke</span></a>
</span></b>
<pre>(In reply to Danylo from <a href="show_bug.cgi?id=104297#c39">comment #39</a>)
<span class="quote">> Created <span class=""><a href="attachment.cgi?id=143012" name="attach_143012" title="Shader test to reporduce TCS vec4 issue">attachment 143012</a> <a href="attachment.cgi?id=143012&action=edit" title="Shader test to reporduce TCS vec4 issue">[details]</a></span>
> Shader test to reporduce TCS vec4 issue</span >
For what it's worth, hacking the DEBUG_SPILL_VEC4 code to do:
if (no_spill[i] || i != 42)
continue;
will still reproduce the problem on Kabylake with INTEL_SCALAR_TCS=0
INTEL_DEBUG=spill_vec4, but it only spills and fills a single register. That
spill/fill appears to be working in the simulator, too - the value read back
matches the value written.</pre>
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