[Bug 70117] New: [ivb cpu edp] clock recovery fails with too many full/voltage retries, channel equalization succeeds

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=70117

          Priority: medium
            Bug ID: 70117
                CC: intel-gfx-bugs at lists.freedesktop.org
          Assignee: intel-gfx-bugs at lists.freedesktop.org
           Summary: [ivb cpu edp] clock recovery fails with too many
                    full/voltage retries, channel equalization succeeds
        QA Contact: intel-gfx-bugs at lists.freedesktop.org
          Severity: normal
    Classification: Unclassified
                OS: All
          Reporter: jani.nikula at intel.com
          Hardware: Other
            Status: NEW
           Version: unspecified
         Component: DRM/Intel
           Product: DRI

There are a number of IVB cpu eDP machines (such as Dell XPS 13, Asus TX300,
Asus UX32VD, others) out there that fail the clock recovery phase of DP link
training with "too many full/voltage retries, give up", but (as we ignore the
error) pass the link training in the channel equalization phase.

There are plenty of dmesg logs exhibiting the behaviour attached to [1], [2]. A
typical example snippet below.

[    2.924336] [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
[    2.924341] [drm:ironlake_wait_panel_power_cycle], Wait for panel power
cycle
[    2.924347] [drm:ironlake_wait_panel_status], mask b800000f value 00000000
status 00000000 control abcd0000
[    2.924355] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000
PP_CONTROL: 0xabcd0008
[    2.924358] [drm:ironlake_edp_panel_vdd_on], eDP was not running
[    3.128336] [drm:intel_dp_set_signal_levels], Using signal levels 09000000
[    3.128969] [drm:intel_dp_set_signal_levels], Using signal levels 0c000000
[    3.129598] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000
[    3.130225] [drm:intel_dp_set_signal_levels], Using signal levels 09000000
[    3.130849] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000
[    3.131478] [drm:intel_dp_set_signal_levels], Using signal levels 09000000
[    3.132104] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000
[    3.132726] [drm:intel_dp_set_signal_levels], Using signal levels 09000000
[    3.133349] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000
[    3.133971] [drm:intel_dp_set_signal_levels], Using signal levels 09000000
[    3.134595] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000
[    3.135223] [drm:intel_dp_start_link_train], too many full retries, give up
[    3.135225] [drm:ironlake_edp_panel_on], Turn eDP power on
[    3.135228] [drm:ironlake_wait_panel_power_cycle], Wait for panel power
cycle
[    3.135234] [drm:ironlake_wait_panel_status], mask b800000f value 00000000
status 00000000 control abcd0008
[    3.135239] [drm:ironlake_wait_panel_on], Wait for panel power on
[    3.135243] [drm:ironlake_wait_panel_status], mask b000000f value 80000008
status 0000000a control abcd000b
[    3.348075] [drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1
[    3.348083] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0xabcd000b
PP_CONTROL: 0x80000008
[    3.368420] [drm:intel_enable_rc6], RC6 and deep RC6 enabled
[    3.368421] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
[    3.381445] [drm:gen6_enable_rps], Overclocking supported. Max: 1200MHz,
Overclock max: 1200MHz
[    3.401461] [drm:intel_dp_set_signal_levels], Using signal levels 0e000000
[    3.402398] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training
successful

This patch fixes the issue, and clock recovery passes at first attempt, but I
don't think this is entirely correct:

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1b74275..71f6ae4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1800,9 +1800,9 @@ static void intel_enable_dp(struct intel_encoder
*encoder)

     ironlake_edp_panel_vdd_on(intel_dp);
     intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
-    intel_dp_start_link_train(intel_dp);
     ironlake_edp_panel_on(intel_dp);
     ironlake_edp_panel_vdd_off(intel_dp, true);
+    intel_dp_start_link_train(intel_dp);
     intel_dp_complete_link_train(intel_dp);
     intel_dp_stop_link_train(intel_dp);
 }

We need to verify our VDD force handling respects power sequencing.

[1] https://bugzilla.kernel.org/show_bug.cgi?id=59841
[2] https://bugs.freedesktop.org/show_bug.cgi?id=64880

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