[Bug 70254] [snb dp hotplug] Pipe B, PCH transcoder B FIFO underrun

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=70254

--- Comment #29 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
Created attachment 92540
  --> https://bugs.freedesktop.org/attachment.cgi?id=92540&action=edit
Patch to allow changing watermark latency values

This patch allows changing the latency values we use for computing the
watermarks.

It adds three new debugfs files. "i915_pri_wm_latency" being the one we're
interested in here.

Reading the file should give similar output as the kernel log had. So in this
case it should look like this:

# cat i915_pri_wm_latency
Primary WM0 latency 7 (0.7 usec)
Primary WM1 latency 3 (1.5 usec)
Primary WM2 latency 4 (2.0 usec)
Primary WM3 latency 22 (11.0 usec)

What you could then do is write new latency values to the file. Let's say we
try to double the latency values:
# echo '14 6 8 44' > i915_pri_wm_latency

Now reading the file again should show the new values. To actually make the
system use them you'd need to force a modeset on all the displays.
"xset dpms force off; xset dpms force on" should be enough for that. After this
is done you should see some change in the 0x45100 and 0x45104 registers.

And then it should just be a matter of trying to cause another underrun, and
increasing the latency values until they no longer occur.

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