[Bug 70254] [snb dp hotplug] Pipe B, PCH transcoder B FIFO underrun

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=70254

--- Comment #35 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
(In reply to comment #34)
> Ok, so it looks like I have this now.
> 
> root at rnavarro-thinkpad:/sys/kernel/debug/dri/0# cat i915_pri_wm_latency
> WM0 7 (0.7 usec)
> WM1 3 (1.5 usec)
> WM2 4 (2.0 usec)
> WM3 22 (11.0 usec)
> 
> root at rnavarro-thinkpad:/sys/kernel/debug/dri/0# echo '14 6 8 44' >
> i915_pri_wm_latency
> 
> root at rnavarro-thinkpad:/sys/kernel/debug/dri/0# cat i915_pri_wm_latency
> WM0 14 (1.4 usec)
> WM1 6 (3.0 usec)
> WM2 8 (4.0 usec)
> WM3 44 (22.0 usec)
> 
> Ran the commands just as described, would it make sense to figure out what
> the minimums are?

I guess we can try to narrow it down as much as possible. If the doubled values
work, then we could bisect it further to find the smallest acceptable value. If
the doubled values didn't work, might want to try 3x,4x,5x...

> 
> Does it matter which WMx I'm changing?

With two displays only WM0 will be used. The others only kick in to provide
more power savings in single display use cases.

> 
> Should I change them all at the same time as described, or one by one?

Probably best to keep changing all in sync for now. I think we at least need to
maintain the relationship WM0<=WM1<=WM2<=WM3 (for the usec values).

Also probably a good idea to check at each step that the change resulted in a
corresponding change to the 0x45100 and 0x45104 register values. In your two
display case, those two registers should always have an identical value to each
other.

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