[Bug 80081] [HSW Bisected]igt/pm_rpm/system-suspend cause " WARNING: CPU: 7 PID: 786 at drivers/gpu/drm/i915/i915_gem.c:1644 i915_gem_release_all_mmaps+0x28/0x7e [i915]()

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=80081

Guo Jinxian <jinxianx.guo at intel.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[HSW                        |[HSW
                   |Regression]igt/pm_rpm/syste |Bisected]igt/pm_rpm/system-
                   |m-suspend cause " WARNING:  |suspend cause " WARNING:
                   |CPU: 7 PID: 786 at          |CPU: 7 PID: 786 at
                   |drivers/gpu/drm/i915/i915_g |drivers/gpu/drm/i915/i915_g
                   |em.c:1644                   |em.c:1644
                   |i915_gem_release_all_mmaps+ |i915_gem_release_all_mmaps+
                   |0x28/0x7e [i915]()"         |0x28/0x7e [i915]()
           Keywords|bisect_pending              |

--- Comment #1 from Guo Jinxian <jinxianx.guo at intel.com> ---
fe5b1886a78d92e0e4681e449725714e947dfc58 is the first bad commit
commit fe5b1886a78d92e0e4681e449725714e947dfc58
Author:     Imre Deak <imre.deak at intel.com>
AuthorDate: Mon May 12 18:35:05 2014 +0300
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Thu May 22 21:53:27 2014 +0200

    drm/i915: disable GT power saving early during system suspend

    Atm, we disable GT power saving during the end of the suspend sequence
    in i915_save_state(). Doing the disabling at that point seems arbitrary.
    One reason to disable it early though is to have a quiescent HW state
    before we do anything else (for example save registers). So move the
    disabling earlier, which also takes care canceling of the deferred RPS
    enabling work done by intel_disable_gt_powersave().

    Note that after the move we'll call intel_disable_gt_powersave() only
    in case modeset is enabled, but that's anyway the only case where we
    have it enabled in the first place.

    Signed-off-by: Imre Deak <imre.deak at intel.com>
    Reviewed-by: Robert Beckett <robert.beckett at intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

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