[Bug 74861] [hsw regression] Fast audio playback on Intel Haswell HDMI due to runtime pm

[bugzilla-daemon at bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=74861

Mengdong Lin <mengdong.lin at intel.com> changed:

           What    |Removed                     |Added
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                 CC|                            |mengdong.lin at intel.com

--- Comment #39 from Mengdong Lin <mengdong.lin at intel.com> ---
Created attachment 140991
  --> https://bugzilla.kernel.org/attachment.cgi?id=140991&action=edit
Patch to restore valid M/V value to covert BCLK from CDCLK

Could you try if the attached patch can solve this faster playback rate issue
on Haswell?

We observed the same problem on Broadwell: if the display power well is turn
off during display mode change or for power saving, then audio playback rate
will become ~20% faster. The root cause is the HD-A link BCLK is converted from
Core Display Clock CDCLK. The default M/N value is for 450Mhz CDCLk to generate
24Mhz BCLK. BIOS can choose 540Mhz CDCLK (~20% than 450Mhz) and progrm M/N
value accordingly. But the M/N value registers will fall back to default value
after the display power well is turn off. So later the BCLK will be ~20% faster
than 24Mhz and result in a faster playback rate. So the patch is to save and
restore valid M/N value on controller suspend/resume (i.e. when release/request
display power well).

Thanks
Mengdong

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