[Bug 71701] Regression, Dual-Head, i915 mode-setting driver, "pipe B stuck"

[bugzilla-daemon at bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=71701

--- Comment #4 from Kris Karas <bugs-a13 at moonlit-rail.com> ---
OK, bisecting isn't really necessary, as there are only four commits in
patch-3.13.6 related to i915.  Easy enough to try 'em all!  :-)

Got it!  The problem is split across two commits:
    05524f5b61c3c15859477a2165cff81e3d682743, and
    12b96a3843431abcb29fe8f2cd04f17e32366de0
Backing out the first is sufficient to restore my dual-head display to proper
function.  I have no idea why adjusting cache-line alignment (presumably we
mean "aligning" the cache-line?) would break things.  I guess the real issue is
somewhat deeper in the logic.

I'm typing this on 3.13.6 with the first of those commits backed out, both
displays working nicely.

As the commit is fairly small, I'll post it here in its entirety:

===============================================================================

>From 05524f5b61c3c15859477a2165cff81e3d682743 Mon Sep 17 00:00:00 2001
From: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Tue, 11 Feb 2014 17:52:06 +0000
Subject: drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

commit f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 upstream.

According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.

v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)

Cc: Bjoern C <lkml at call-home.ch>
Cc: Alexandru DAMIAN <alexandru.damian at intel.com>
Cc: Enrico Tagliavini <enrico.tagliavini at gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: stable at vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>

---
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2bde35d..3c5ff7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8335,6 +8335,20 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
        if (ring->id == RCS)
                len += 6;                                                       

+       /*                                                                      
+        * BSpec MI_DISPLAY_FLIP for IVB:                                       
+        * "The full packet must be contained within the same cache line."      
+        *                                                                      
+        * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same        
+        * cacheline, if we ever start emitting more commands before            
+        * the MI_DISPLAY_FLIP we may need to first emit everything else,       
+        * then do the cacheline alignment, and finally emit the                
+        * MI_DISPLAY_FLIP.                                                     
+        */                                                                     
+       ret = intel_ring_cacheline_align(ring);                                 
+       if (ret)                                                                
+               goto err_unpin;                                                 
+                                                                               
        ret = intel_ring_begin(ring, len);                                      
        if (ret)                                                                
                goto err_unpin;                                                 
--                                                                              
cgit v0.9.2

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