[Bug 76150] New: [IVB/HSW Bisected]igt/kms_cursor_crc kms_plane and kms_pipe_crc_basic timeout

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=76150

          Priority: high
            Bug ID: 76150
                CC: intel-gfx-bugs at lists.freedesktop.org
          Assignee: daniel at ffwll.ch
           Summary: [IVB/HSW Bisected]igt/kms_cursor_crc kms_plane and
                    kms_pipe_crc_basic timeout
        QA Contact: intel-gfx-bugs at lists.freedesktop.org
          Severity: major
    Classification: Unclassified
                OS: Linux (All)
          Reporter: huax.lu at intel.com
          Hardware: All
            Status: NEW
           Version: unspecified
         Component: DRM/Intel
           Product: DRI

Created attachment 95767
  --> https://bugs.freedesktop.org/attachment.cgi?id=95767&action=edit
dmesg

System Environment:
--------------------------
Platform: Ivybridge/Haswell
Kernel:  drm-intel-fixes/5c673b60a9b3b23486f4eda75c72e91d31d26a2b

Bug detailed description:
-----------------------------
kms_cursor_crc kms_plane and kms_pipe_crc_basic are timeout on Ivybridge and
Haswell with -nightly and -fixes kernel. They work well on -queued kernel.

Bisect shows: 5c673b60a9b3b23486f4eda75c72e91d31d26a2b is the first bad commit
commit 5c673b60a9b3b23486f4eda75c72e91d31d26a2b
Author:     Daniel Vetter <daniel.vetter at ffwll.ch>
AuthorDate: Fri Mar 7 20:34:46 2014 +0100
Commit:     Jani Nikula <jani.nikula at intel.com>
CommitDate: Wed Mar 12 17:20:34 2014 +0200

    drm/i915: Don't enable display error interrupts from the start

    We need to enable interrupt processing before all the modeset
    state is set up. But that means we can fall over when we get a pipe
    underrun. This shouldn't happen as long as the bios works correctly
    but as usual this turns out to be wishful thinking.

    So disable error interrupts at irq install time and rely on the
    re-enabling code in the modeset functions to take care of this.

    Note that due to the SDE interrupt handling race we must
    uncondtionally enable all interrupt sources in SDEIER, hence no need
    to enable the SERR bit specifically.

    On gmch platforms we don't have an explicit enable/mask bit for fifo
    underruns. Fixing this up would require a bit of software tracking,
    hence is material for a separate patch. To make this possible we need
    to switch all gmch platforms to the new pipestat interrupt handling
    scheme Imre implemented for vlv, and then also add a safe form of sw
    state checking to __cpu_fifo_underrun_reporting_enabled a bit.

    v2: Also handle the ilk/snb cpu fifo underrun bits accordingly.
    Spotted by Ville.

    v3: Also handle the south interrupt underrun bits on ibx. Again
    spotted by Ville.

    Reported-by: Rob Clark <robdclark at gmail.com>
    Cc: Rob Clark <robdclark at gmail.com>
    Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
    Cc: stable at vger.kernel.org
    Tested-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
    Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
    Signed-off-by: Jani Nikula <jani.nikula at intel.com>


run ./kms_cursor_crc --run-subtest cursor-black-visible-offscreen
output:
IGT-Version: 1.5-g9812768 (x86_64) (Linux:
3.14.0-rc5_drm-intel-fixes_5c673b_20140313+ x86_64)

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