[Bug 85576] [BDW] i915.enable_ppgtt=0 causes graphical corruption

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=85576

--- Comment #4 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
(In reply to Chris Wilson from comment #3)
> The issue is that the cache setting bits in the Global GTT PTE are ignored.
> At best we can throw a warning that setting i915.enable_ppgtt=0 is a bad
> idea, or we might be able to disable the render caches using a debug
> register. Fundamentally though it is a CANTFIX/WONTFIX.

Is the problem caused by this nice piece if hardware design?
"***For GGTT, there is NO pat_sel[2:0] from the entry, so RTL will always use
the value corresponding to pat_sel = 000***"

If so then I think we might need to make PAT entry 0 UC, which is a bit sad
since it's the opposite of how the CPU PAT is set up, but at least it would
give correct behaviour. The only concern is that all GGTT accesses will then be
UC which I suppose could lead to some performance issues. But MOCS can still
override it so anything that has MOCS could still get WB if needed.

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