[Bug 91410] [BDW][Audio][HD-A Display] DP/HDMI audio playback abnormal

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=91410

--- Comment #3 from Lu, Han <han.lu at intel.com> ---
Hi Jesse,

This issue is easy to reproduce on one BDW RVP but not easy to reproduce on
other platforms. It may not an universal issue, yet we are confused about how
incorrect cd_clock be passed to audio. (in normal case cbclk should be 337500
right?)

My test result with intel_reg:
# ./intel_reg read 0x46200
                                    (0x00046200): 0x000002a2
from Bspec I'm not sure what this value stands for;
# ./intel_reg read 0x130040
                          LCPLL_CTL (0x00130040): 0x48000000
for Bspec it looks like 337.5MHz and X2 CD clock be set? 

and from dmesg:
# dmesg | grep lh
[    1.386837] lh: hda need i915_power?[1]
[    1.386840] lh: cbclk: 675000


my debug patch in kernel, FYI:

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index ca151b4..66ae510 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -820,10 +820,12 @@ static void haswell_set_bclk(struct hda_intel *hda)
     int cdclk_freq;
     unsigned int bclk_m, bclk_n;

+    printk("lh: hda need i915_power?[%d]\n", hda->need_i915_power);
     if (!hda->need_i915_power)
         return;

     cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
+    printk("lh: cbclk: %d\n", cdclk_freq);
     switch (cdclk_freq) {
     case 337500:
         bclk_m = 16;

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