[Bug 89419] [SKL][Audio][HD-A Display]: Can't detect Display audio codec if not connect HDMI and DP monitor when boot up

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=89419

jinliangx.wang at intel.com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEEDINFO                    |ASSIGNED

--- Comment #6 from jinliangx.wang at intel.com ---
Bisect from drm-intel-next-queued kernel tree.

The first bad commit should be:
commit 94dd5138c5ed02d26982d9704e8c1e9d72e20b40
Author:     Satheeshakrishna M <satheeshakrishna.m at intel.com>
AuthorDate: Wed Feb 4 13:57:44 2015 +0000
Commit:     Daniel Vetter <daniel.vetter at ffwll.ch>
CommitDate: Fri Feb 13 23:28:01 2015 +0100

    drm/i915/skl: Implementation of SKL display power well support

    This patch implements core logic of SKL display power well.

    v2: Addressed Imre's comments
        - Added respective DDIs under power well #1 and #2
        - Simplified repetitive code in power well programming

    v3: Implemented Imre's comments
        - Further simplified power well programming
        - Made sure that PW 1 is enabled prior to PW 2

    v4: Fix minor conflict with the the cherryview support (Damien)

    v5: Add the PLL power domain to the always on power well (Damien)

    v6: Disable BIOS power well (Imre)
        Use power well data for comparison (Imre)
        Put the PLL power domain into PW1 as its needed for CDCLK (Satheesh,
        Damien)

    v7: Addressed Imre's comments
      - Lowered the time out to 1ms
      - Added parantheses in macro
      - Moved debug message and fixed wait_for interval

    v8:
      - Add a WARN() when swiching on an unknown power well (Imre, done by
Damien)
      - Whitespace fixes (spaces instead of tabs) (Damien)

    v9: (Imre, done by Damien)
      - Merge the register definitions with this patch
      - Merge the MISC IO power well in this patch

    v10: (Imre, done by Damien)

      - Define the Misc I/O power domains to be the power well 1 ones as Misc
I/O
        needs to be enabled with PW1
      - Added Transcoder A and VGA domains to PW 2
      - Remove the MISC_IO power domains as well in the the always on
        domains definition
      - Move Misc I/O power well at the top of the power well list so it's
turned
        on right after PW1.

    Reviewed-by: Imre Deak <imre.deak at intel.com>
    Signed-off-by: Satheeshakrishna M <satheeshakrishna.m at intel.com> (v3,v6,v7)
    Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
    Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

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