[Bug 89124] [SKL mobile] igt/kms_psr_sink_crc subcases fail if PSR enabled

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=89124

--- Comment #6 from cprigent <christophe.prigent at intel.com> ---
Following tests are fail on SKL-Y with last setup:
igt at kms_psr_sink_crc@cursor_blt
igt at kms_psr_sink_crc@cursor_mmap_gtt
igt at kms_psr_sink_crc@cursor_mmap_gtt_waiting
igt at kms_psr_sink_crc@cursor_plane_onoff
igt at kms_psr_sink_crc@cursor_render
igt at kms_psr_sink_crc@primary_mmap_cpu
igt at kms_psr_sink_crc@primary_mmap_gtt
igt at kms_psr_sink_crc@primary_mmap_gtt_waiting
igt at kms_psr_sink_crc@primary_page_flip
igt at kms_psr_sink_crc@primary_render
igt at kms_psr_sink_crc@sprite_blt
igt at kms_psr_sink_crc@sprite_mmap_cpu
igt at kms_psr_sink_crc@sprite_mmap_gtt
igt at kms_psr_sink_crc@sprite_mmap_gtt_waiting
igt at kms_psr_sink_crc@sprite_plane_move
igt at kms_psr_sink_crc@sprite_plane_onoff
igt at kms_psr_sink_crc@sprite_render

Platform: SKY LAKE Y A0 
CPU : Intel(R) Core(TM) m5-6Y57 CPU @ 1.10GHz (family: 6, model: 78  stepping:
3)
MCP : SKL-Y  D1 2+2 (ou ULX-D1)
QDF : QJK9 
CPU : SKL D0
Chipset PCH: Sunrise Point LP C1       
CRB : SKY LAKE Y LPDDR3 RVP3 CRB FAB2
Reworks : All Mandatories + FBS02,FBS03, F23, O-02 & O-06
BIOS : SKLSE2R1.R00.X097.B02.1509020030
ME FW : 11.0.0.1173
Ksc (EC FW): 1.19

Linux distribution: Ubuntu 14.04 LTS 64 bits
kernel 4.3.0-rc4-drm-intel-nightly+ c38f2c24fb6484fc6900efa6f8d968e8ee964e9c
from git://anongit.freedesktop.org/drm-intel
Mesa - 11.0.3 from http://cgit.freedesktop.org/mesa/mesa/
xf86-video-intel - 2.99.917 from
http://cgit.freedesktop.org/xorg/driver/xf86-video-intel/
Libdrm - 2.4.65 from http://cgit.freedesktop.org/mesa/drm/
Libva - 1.6.1 from http://cgit.freedesktop.org/libva/
vaapi intel-driver - 1.6.1 from http://cgit.freedesktop.org/vaapi/intel-driver
Cairo - 1.14.2 from http://cgit.freedesktop.org/cairo
Xorg Xserver - 1.17.2 from http://cgit.freedesktop.org/xorg/xserver

commit c38f2c24fb6484fc6900efa6f8d968e8ee964e9c
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date:   Fri Oct 9 14:50:43 2015 +0200
drm-intel-nightly: 2015y-10m-09d-12h-49m-56s UTC integration manifest

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