[Bug 91410] [BDW][Audio][HD-A Display] DP/HDMI audio playback abnormal

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=91410

--- Comment #26 from Jani Nikula <jani.nikula at intel.com> ---
We have the function to query cdclk frequency because the audio registers em4/5
are lost if the display power domains go to power save. If my memory serves me
right the function to query cdclk frequency predates the ability to change
cdclk frequency. It's likely the audio driver only queries cdclk whenever the
em4/5 registers may have been lost, and we don't communicate cdclk changes.

Sadly, there's no dmesg with drm.debug=14 to see if there actually are any
cdclk changes in the cases in question, or if that's just another theoretical
case I came up in addition!

I guess we should also do

diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 56ba8765816e..1063108a9bab 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -624,17 +624,11 @@ static void
i915_audio_component_codec_wake_override(struct device *dev,
 static int i915_audio_component_get_cdclk_freq(struct device *dev)
 {
     struct drm_i915_private *dev_priv = dev_to_i915(dev);
-    int ret;

     if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
         return -ENODEV;

-    intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
-    ret = dev_priv->display.get_display_clock_speed(dev_priv->dev);
-
-    intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
-
-    return ret;
+    return dev_priv->cdclk_freq;
 }

 static int i915_audio_component_sync_audio_rate(struct device *dev,

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