[Bug 95207] New: [SKL] 5k tiled display issues (dual DP)
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Fri Apr 29 13:00:05 UTC 2016
https://bugs.freedesktop.org/show_bug.cgi?id=95207
Bug ID: 95207
Summary: [SKL] 5k tiled display issues (dual DP)
Product: DRI
Version: DRI git
Hardware: x86-64 (AMD64)
OS: All
Status: NEW
Severity: normal
Priority: medium
Component: DRM/Intel
Assignee: intel-gfx-bugs at lists.freedesktop.org
Reporter: bugs at bzatek.net
QA Contact: intel-gfx-bugs at lists.freedesktop.org
CC: intel-gfx-bugs at lists.freedesktop.org
Created attachment 123345
--> https://bugs.freedesktop.org/attachment.cgi?id=123345&action=edit
dmesg drm.debug=0x1e (4.6.0-rc5-g1101e5f, 2016y-04m-28d-16h-43m-10s UTC)
I'm fighting to get native 5k display working, kindly asking for debugging
instructions or hints. This is Dell UP2715K, connected via two native DP ports
on a C236 board (SunrisePoint PCH) running Skylake E3-1275v5 CPU. Note that I
can get native resolution under Windows 7 just fine, ruling out HW
incompatibility.
kernel 4.6.0-rc5-g1101e5f, drm-intel-nightly branch 2016y-04m-28d-16h-43m-10s
UTC
xorg-server git as of 2016-04-28
xf86-video-intel git as of 2016-04-28
libdrm git as of 2016-04-28
Presumably this is a tiled display with two 2560x2880 at 60 tiles, one for each DP
port.
First problem: native resolution is not detected, only fallback modelines are
generated. The display falls back to 2560x1440 on a first port and 848x480 on
the second as parsed from EDID. Interesting parts of the drm.debug=0x1e log:
> [ 0.602822] [drm:intel_update_max_cdclk] Max dotclock rate: 675000 kHz
> [ 0.969823] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1]
> [ 0.969824] [drm:intel_dp_detect] [CONNECTOR:42:DP-1]
> [ 0.970368] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 00 01 83 02 02 06 00 00 00 00
> [ 0.970895] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
> [ 0.970897] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
> [ 0.970898] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
> [ 0.970903] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
> [ 0.971318] [drm:intel_dp_probe_oui] Sink OUI: 000000
> [ 0.971790] [drm:intel_dp_probe_oui] Branch OUI: 000000
> [ 0.972192] [drm:intel_dp_probe_mst] Sink is not MST capable
> [ 0.983910] [drm:drm_parse_display_id] base revision 0x12, length 121, 0 0
> [ 0.983938] [drm:drm_parse_display_id] block id 18, rev 0, len 22
> [ 0.983939] [drm:drm_parse_display_id] tile cap 0x82
> [ 0.983939] [drm:drm_parse_display_id] tile_size 2560 x 2880
> [ 0.983940] [drm:drm_parse_display_id] topo num tiles 2x1, location 1x0
> [ 0.983941] [drm:drm_parse_display_id] vend DEL
> [ 0.984617] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1] status updated from unknown to connected
> [ 0.984809] [drm:drm_edid_to_eld] ELD monitor DELL UP2715K
> [ 0.984810] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
> [ 0.984813] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:42:DP-1] probed modes :
> [ 0.984815] [drm:drm_mode_debug_printmodeline] Modeline 59:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x48 0x9
> [ 0.984816] [drm:drm_mode_debug_printmodeline] Modeline 60:"3840x2160" 60 533250 3840 3920 3952 4000 2160 2214 2219 2222 0x40 0xa
> [ 0.984817] [drm:drm_mode_debug_printmodeline] Modeline 64:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
> [ 0.984818] [drm:drm_mode_debug_printmodeline] Modeline 67:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
> [ 0.984819] [drm:drm_mode_debug_printmodeline] Modeline 65:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
> [ 0.984820] [drm:drm_mode_debug_printmodeline] Modeline 63:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
> [ 0.984821] [drm:drm_mode_debug_printmodeline] Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
> [ 0.984822] [drm:drm_mode_debug_printmodeline] Modeline 62:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
> [ 0.984823] [drm:drm_mode_debug_printmodeline] Modeline 70:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
> [ 0.984824] [drm:drm_mode_debug_printmodeline] Modeline 68:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
> [ 0.984825] [drm:drm_mode_debug_printmodeline] Modeline 71:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
> [ 0.984826] [drm:drm_mode_debug_printmodeline] Modeline 69:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
> [ 0.985499] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2]
> [ 0.985499] [drm:intel_dp_detect] [CONNECTOR:48:DP-2]
> [ 0.986218] [drm:intel_dp_get_dpcd] DPCD: 12 14 c4 01 01 00 01 83 02 02 06 00 00 00 00
> [ 0.986731] [drm:intel_dp_get_dpcd] Display Port TPS3 support: source yes, sink yes
> [ 0.986732] [drm:intel_dp_print_rates] source rates: 162000, 216000, 270000, 324000, 432000, 540000
> [ 0.986733] [drm:intel_dp_print_rates] sink rates: 162000, 270000, 540000
> [ 0.986734] [drm:intel_dp_print_rates] common rates: 162000, 270000, 540000
> [ 0.987181] [drm:intel_dp_probe_oui] Sink OUI: 000000
> [ 0.987622] [drm:intel_dp_probe_oui] Branch OUI: 000000
> [ 0.988100] [drm:intel_dp_probe_mst] Sink is not MST capable
> [ 0.996162] [drm:drm_parse_display_id] base revision 0x12, length 121, 0 0
> [ 0.996163] [drm:drm_parse_display_id] block id 18, rev 0, len 22
> [ 0.996164] [drm:drm_parse_display_id] tile cap 0x80
> [ 0.996165] [drm:drm_parse_display_id] tile_size 2560 x 2880
> [ 0.996165] [drm:drm_parse_display_id] topo num tiles 2x1, location 0x0
> [ 0.996183] [drm:drm_parse_display_id] vend DEL
> [ 0.996909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2] status updated from unknown to connected
> [ 0.996944] [drm:drm_edid_to_eld] ELD: no CEA Extension found
> [ 0.996945] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-2] probed modes :
> [ 0.996947] [drm:drm_mode_debug_printmodeline] Modeline 72:"848x480" 60 29750 848 896 928 1008 480 483 488 494 0x48 0x9
This confirms tile setup and proper dimensions. Could the issue here be that
the mode corresponding to the tile size is not included in the EDID data?
Second problem: trying custom modelines. Generated using `cvt` with reduced
blanking, pixel clock is within limits:
> [ 3.237] (II) intel(0): EDID for output DP1
> [ 3.237] (II) intel(0): Max Image Size [cm]: horiz.: 60 vert.: 34
> [ 3.237] (II) intel(0): Ranges: V min: 29 V max: 75 Hz, H min: 31 H max: 180 kHz, PixClock max 545 MHz
> [ 3.237] (II) intel(0): Modeline "2560x2880"x60.0 483.25 2560 2608 2640 2720 2880 2883 2893 2962 +hsync -vsync (177.7 kHz UP)
...
> [ 3.360] (II) intel(0): switch to mode 2560x2880 at 60.0 on DP1 using pipe 0, position (0, 0), rotation normal, reflection none
> [ 3.360] (II) intel(0): switch to mode 2560x2880 at 60.0 on DP2 using pipe 1, position (0, 0), rotation normal, reflection none
> [ 3.360] (II) intel(0): Setting screen physical size to 677 x 762
(^^ this is running an X login manager with cloned screen)
> [ 17.940] (II) intel(0): resizing framebuffer to 5120x2917
> [ 17.977] (II) intel(0): switch to mode 2560x2880 at 60.0 on DP1 using pipe 0, position (2560, 0), rotation normal, reflection none
> [ 17.979] (II) intel(0): switch to mode 2560x2880 at 60.0 on DP2 using pipe 1, position (0, 37), rotation normal, reflection none
(^^ this is after manual randr correction) - the 2917 px height looks
suspicious
This actually results in some image, tiles are aligned side by side. However
resulting image is garbled, torn in several pieces, weird colours etc. Seems to
be panel issue itself resulting from wrong timings as OSD menu is also
mispositioned and broken. Note that with vanilla 4.6.0-rc5 I cannot get any
image so there's something in the drm-intel-nightly branch that enables at
least the garbled image. Almost there...
Could the problem be that I'm trying to push independent screens on two DP
ports that are out of sync? Does the DP tiling need to be configured specially?
I've tried different modelines, increasing pixel clock, blanking intervals,
etc. with no difference.
Third problem: perhaps unrelated, reported already in other bugs:
> [ 1.059275] [drm:intel_enable_pipe] enabling pipe A
...
> [ 1.078707] [drm:intel_dp_link_training_channel_equalization] Channel EQ done. DP Training successful
> [ 1.078949] [drm:skylake_pfit_enable] for crtc_state = ffff880809299800
> [ 1.079296] ------------[ cut here ]------------
> [ 1.079298] WARNING: CPU: 1 PID: 6 at drivers/gpu/drm/i915/intel_pm.c:3647 skl_update_other_pipe_wm+0x10f/0x120
> [ 1.079299] WARN_ON(!wm_changed)
...
> [ 1.079310] [<ffffffff81421f4f>] ? skl_update_other_pipe_wm+0x10f/0x120
> [ 1.079311] [<ffffffff814220a4>] ? skl_update_wm+0x144/0x590
> [ 1.079313] [<ffffffff814ab1f7>] ? intel_ddi_enable_transcoder_func+0x167/0x230
> [ 1.079314] [<ffffffff8148eb61>] ? haswell_crtc_enable+0x741/0x8c0
...
Attached is dmesg with drm.debug=0x1e, Xorg.0.log will follow.
Let me know if you want me to test any patches. Thanks!
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