[Bug 92878] eDP link clock recovery fails with *ERROR* too many full retries, give up

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=92878

--- Comment #15 from Ander Conselvan de Oliveira <conselvan2 at gmail.com> ---
(In reply to Ander Conselvan de Oliveira from comment #12)
> This could be related to an issue Sivakumar  once mentioned, that the driver
> handles the request from the sink wrong, using the maximum supported
> pre-emphasis for the requested voltage swing, instead of using the requested
> pre-emphasis with the maximum support vswing.

[  204.649626] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
[  204.649627] [drm:intel_dp_set_signal_levels] Using vswing level 0
[  204.649628] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
[  204.650229] [drm:intel_dp_link_training_clock_recovery] link status: 00 00
80 00 66 66
[  204.650230] [drm:intel_dp_set_signal_levels] Using signal levels 08000000
[  204.650231] [drm:intel_dp_set_signal_levels] Using vswing level 2
[  204.650231] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
[  204.650813] [drm:intel_dp_link_training_clock_recovery] link status: 00 00
00 00 66 66

Unfortunately that's not the issue. The sink really does request vswing 2 and
pre emphasis 1. One interesting thing is in the first try the
LINK_STATUS_UPDATED bit is set. It is clear in all other attempts. I wonder if
the device expects us to iterate at max voltage.

Another possibility is that the hardware is just not programmed correctly, so
the signal the sink expects is not going through the link. That would help
explain bug 93517 too.

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