[Bug 89493] [SKL] sporadic "missed interrupts"

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=89493

Chris Wilson <chris at chris-wilson.co.uk> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|REOPENED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #6 from Chris Wilson <chris at chris-wilson.co.uk> ---
commit 7c17d377374ddbcfb7873366559fc4ed8b296e11
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Wed Jan 20 15:43:35 2016 +0200

    drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists

    Broadwell and later currently use the same unordered command sequence to
    update the seqno in the HWS status page and then assert the user
    interrupt. We should apply the w/a from legacy (where we do an mmio
    read to delay the seqno read after the interrupt), but this is not
    enough to enforce coherent seqno visibilty on Skylake. Rather than
    search for the proper post-interrupt seqno barrier, use a strongly
    ordered command sequence to write the seqno, then assert the user
    interrupt from the ring.

    v2: Move around the wa tail dwords to avoid adding duplicate code.

    v3: Add references, comments on workarounds and bit5 check.

    References: https://bugs.freedesktop.org/show_bug.cgi?id=93693
    Testcase: igt/gem_ring_sync_loop #skl
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Cc: Mika Kuoppala <mika.kuoppala at intel.com>
    Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>
    Link:
http://patchwork.freedesktop.org/patch/msgid/1453297415-17793-1-git-send-email-mika.kuoppala@intel.com

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